MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1217

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.1.3
The eSPI can be programmed to work in a single master environment. This section describes eSPI master
operation in a single-master configuration.
In master mode, the eSPI sends a message to the slave peripheral, which sends back a simultaneous reply.
A single master with multiple slaves uses up to 4 chip select signals to selectively enable slaves, as shown
in
To start exchanging data, the core writes the data to be sent into the SPITF register. The eSPI then generates
programmable clock pulses on SPI_CLK for each character. It shifts Tx data out on the “eSPI master-out
slave-in” (SPI_MOSI) and Rx data in on the eSPI “master-in slave-out” (SPI_MISO) simultaneously.
During the transmission process the core is responsible for supplying the data whenever the eSPI requests
it to ensure smooth operation.
The maximum sustained data rate that the eSPI supports depends on the SW latency. However, the eSPI
can transfer a single character at very high rates— system clock/2 up to a maximum specified by the device
hardware specifications. Gaps might be inserted between multiple frames.
18.2
The eSPI interface consists of transmit, receive, clock and chip selects
Freescale Semiconductor
Figure
18-2.
External Signal Descriptions
Modes of Operation
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Master eSPI
Figure 18-2. Single-Master/Multi-Slave Configuration
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_CS3
SPI_MOSI
SPI_MISO
SPI_CLK
SPISEL
SPI_MOSI
SPI_MISO
SPI_CLK
SPISEL
SPI_MOSI
SPI_MISO
SPI_CLK
SPISEL
Slave 1
Slave 2
Slave 0
Enhanced Serial Peripheral Interface
18-3