MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 809

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.3.5
The RBIFX register provides a set of four 6-bit offsets for locating up to four octets in a received frame
and passing them to the receive queue filer as the user-defined ARB property. Through RBIFX a custom
ARB filer property can be constructed from arbitrary bytes, which allows frame filing on the basis of
bitfields not ordinarily provided to the filer, such as bits from the Ethernet preamble or TCP flags. The
value of property ARB is the concatenation of {B0, B1, B2, B3} to 32-bits, where B0–B3 are the bytes as
defined by RBIFX.
Figure 14-28
receive frame through the FIFO packet interface, a value of BnCTL = 01 is not supported unless
RCTRL[PRSFM]=1 and RCTRL[PRSDEP] is configured to parse L2 packets over the FIFO interface.
Below is a list of arbitrary extraction requirements:
Freescale Semiconductor
Bits
25
26
27
28
29
30
31
•
•
•
•
•
Byte extraction level cannot exceed the parser depth: a value of BnCTL=10 requires
RCTRL[PRSDEP]=1x and a value of BnCTL=11 requires RCTRL[PRSDEP]=11.
For BnCTL = 01, BnOFFSET = 7 is not supported.
For values of BnCTL=10 or BnCTL=11, the controller extracts the defined bytes even if it does not
recognize the L3 or L4 header, respectively.
No L4 extraction is done if a packet is an IPV4 or IPV6 fragment frame.
If no extraction occurs due to BnOFFSET longer than frame data or it is an unsupported
BnOFFSET, the Bn extraction values are filled with zeros.
Name
EN1
EN2
EN3
EN4
EN5
EN6
EN7
describes the definition for the RBIFX register.Note: when the eTSEC is configured to
Receive Bit Field Extract Control Register (RBIFX)
Receive queue 1 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 2 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 3 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 4 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 5 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 6 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
Receive queue 7 enable.
0 RxBD ring is not queried for reception. In effect the receive queue is disabled.
1 RxBD ring is queried for reception.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-32. RQUEUE Field Descriptions (continued)
Description
Enhanced Three-Speed Ethernet Controllers
14-61