MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 352

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Figure 8-54
8.5.7
The DDR memory controller facilitates system design flexibility by providing a write timing adjustment
parameter, write data delay, (TIMING_CFG_2[WR_DATA_DELAY]) for data and DQS. The DDR
SDRAM specification requires DQS be received no sooner than 75% of an SDRAM clock period—and
no later than 125% of a clock period—from the capturing clock edge of the command/address at the
SDRAM. The WR_DATA_DELAY parameter may be used to meet this timing requirement for a variety
of system configurations, ranging from a system with one DIMM to a fully populated system with two
DIMMs. TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and
data from the first clock edge occurring one SDRAM clock cycle after the command is launched. The
delay increment step sizes are in 1/4 SDRAM clock periods starting with the default value of 0.
8-78
DDR SDRAM Write Timing Adjustments
SDRAM Clock
shows the registered DDR SDRAM DIMM single-beat write timing.
MDM[0:7]
MDQS
MRAS
MCAS
MDQ n
MWE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MCS
MA n
Figure 8-54. Registered DDR SDRAM DIMM Burst Write Timing
ROW
0
1
ACTTORW
2
3
COL
4
5
COL
D0
6
D1 D2 D3
7
00
D0
8
D1 D2
9
D3
10
Freescale Semiconductor
11
12