MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1140

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.7.1.2
Software can also program one of the outbound ATMU windows to perform a configuration access. This
is accomplished by programming the ReadTType or WriteTType field of the desired PEXOWAR to 0x2.
Software must only issue 4-byte or less access to the ATMU configuration window and the access cannot
cross a 4-byte boundary. The targeted bus number, targeted device number, targeted function number,
register, and targeted extended register number sent are decoded from the outbound translated PCI Express
address.
A Type 0 configuration cycle is sent to the link if the targeted bus number equals the secondary bus number
(from the type 1 header) and targeted device number is 0. A Type 1 configuration cycle is sent to the link
if targeted bus number does not equal primary bus and secondary bus numbers and it is less than or equal
to the subordinate bus number (from the type 1 header). For all other cases, the PCI Express controller
squashes the write and read results in a response with error returned.
Note that the PCI Express controller does not support access to its internal configuration registers using
the outbound ATMU mechanism. That is, the outbound ATMU mechanism must not be used to program
the internal registers.
17.3.7.2
When the PCI Express controller is configured as an EP device it responds to remote host generated
configuration cycles. This is indicated by decoding the configuration command along with type 0 access
in the packet. A remote host can access all of the PCI Express configuration area except the PCI Express
Controller Internal CSR registers in the extended PCI Express configuration space at offsets
0x400–0x6FF. The PCI Express Controller Internal CSR registers are not accessible by inbound PCI
Express configuration transactions. Attempts to access these registers return all zeros.
While in EP mode, the PCI Express controller does not support generating configuration accesses as a
master. All accesses to PEX_CONFIG_ADDR/PEX_CONFIG_DATA cause the device to access the
internal configuration registers regardless of the targeted bus number or targeted device number
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If the targeted bus number does not equal the PCI Express controller’s bus number, but does equal
the secondary bus number (from the type 1 header) and the targeted device number is 0, then a Type
0 configuration transaction is sent to the PCI Express link.
If the targeted bus number does not equal the PCI Express controller’s bus number, and does not
equal the secondary bus number (from the type 1 header), and the targeted bus number is less than
or equal to the subordinate bus number (from the type 1 header), then a Type 1 configuration
transaction is sent to the PCI Express link.
If none of the above conditions occur, then the PCI Express controller returns all 1s for reads and
ignores writes.
targeted bus number[7:0] = PCI Express address[27:20]
targeted device number[4:0] = PCI Express address[19:15]
targeted function number[2:0] = PCI Express address[14:12]
targeted extended register number[3:0] = PCI Express address[11:8]
targeted register number[5:0] = PCI Express address[7:2]
EP Configuration Register Access
Outbound ATMU Configuration Mechanism (RC-Only)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor