MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 41

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
20.1
20.2
20.2.1
20.3
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.4.7
20.4.8
20.4.9
20.4.10
20.4.11
20.4.12
20.4.13
20.4.14
20.4.15
20.4.16
20.4.17
20.4.18
20.5
20.5.1
20.5.1.1
20.5.1.2
20.5.1.3
20.5.2
20.5.2.1
20.5.2.2
20.5.2.3
20.5.3
20.5.3.1
20.5.3.2
20.5.3.3
20.5.3.4
20.5.4
20.5.5
20.5.6
20.5.7
Freescale Semiconductor
Overview........................................................................................................................ 20-1
Features .......................................................................................................................... 20-2
External Signal Description ........................................................................................... 20-3
Memory Map/Register Definition ................................................................................. 20-5
Functional Description................................................................................................. 20-37
Data Transfer Modes.................................................................................................. 20-3
DMA System Address Register (DSADDR)............................................................. 20-6
Block Attributes Register (BLKATTR)..................................................................... 20-6
Command Argument Register (CMDARG) .............................................................. 20-7
Transfer Type Register (XFERTYP).......................................................................... 20-8
Command Response 0–3 (CMDRSP0–3)................................................................ 20-11
Buffer Data Port Register (DATPORT) ................................................................... 20-12
Present State Register (PRSSTAT) .......................................................................... 20-13
Protocol Control Register (PROCTL) ..................................................................... 20-17
System Control Register (SYSCTL)........................................................................ 20-19
Interrupt Status Register (IRQSTAT)....................................................................... 20-22
Interrupt Status Enable Register (IRQSTATEN) ..................................................... 20-26
Interrupt Signal Enable Register (IRQSIGEN) ....................................................... 20-29
Auto CMD12 Error Status Register (AUTOC12ERR)............................................ 20-31
Host Controller Capabilities (HOSTCAPBLT) ....................................................... 20-33
Watermark Level Register (WML).......................................................................... 20-34
Force Event Register (FEVT) .................................................................................. 20-34
Host Controller Version Register (HOSTVER)....................................................... 20-36
DMA Control Register (DCR)................................................................................. 20-37
Data Buffer .............................................................................................................. 20-38
DMA CCB Interface................................................................................................ 20-40
SD Protocol Unit...................................................................................................... 20-41
Clock & Reset Manager........................................................................................... 20-42
Clock Generator....................................................................................................... 20-43
Card Insertion and Removal Detection.................................................................... 20-43
Power Management and Wake-Up Events .............................................................. 20-43
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Write Operation Sequence ................................................................................... 20-38
Read Operation Sequence.................................................................................... 20-39
Data Buffer Size................................................................................................... 20-39
Internal DMA Request......................................................................................... 20-40
DMA Burst Length .............................................................................................. 20-40
CCB Master Interface .......................................................................................... 20-41
SD Transceiver .................................................................................................... 20-41
SD Clock and Monitor......................................................................................... 20-41
Command Agent.................................................................................................. 20-42
Data Agent ........................................................................................................... 20-42
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