MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1321

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

software_reset()
{
}
20.6.2.3
All cards should be able to establish communication with the host using any operation voltage in the
maximum allowed voltage range specified in this standard. However, the supported minimum and
maximum values for V
whole range. Cards that store the CID (card identification) and CSD data in the preloaded memory are only
able to communicate these information under data transfer V
card have different V
send CSD data.
Therefore, a special command is available:
The voltage validation procedure is designed to provide a mechanism to identify and reject cards which
do not match the V
V
specified range must discontinue any further bus operations and enter the inactive state. By omitting the
voltage range in the command, the host can query each card and determine the common voltage range
before sending out-of-range cards into the inactive state. This query should be used if the host is able to
select a common voltage range or if a notification should be sent to the system when a non-usable cards in
the stack is detected.
20.6.2.4
Card registry on MMC and SD/SD Combo cards are different.
Freescale Semiconductor
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voltage window as the operand of this command. Cards that can not perform data transfer in the
SEND_OP_CONT (CMD1 for MMC),
SD_SEND_OP_CONT (ACMD41 for SD Memory)
set_bit(SYSCTL, RSTA);
set SYSCTL[DTOCV and SDCLKFS];
configure I/O pad;
poll PRSSTAT[CIHB and CDIHB];
set_bit(SYSCTRL, INTIA);
send_command(CMD_GO_IDLE_STATE, <other parameters>); // reset the card with CMD0
or send_command(CMD_IO_RW_DIRECT, <other parameters>);
Voltage Validation
Card Registry
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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Figure 20-26. Flow Chart for Reset of eSDHC and SD I/O Card
range(s) desired by the host. This is accomplished by the host sending the desired
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ranges, the card is not able to complete the identification cycle, nor is it able to
are defined in the operation conditions register (OCR) and may not cover the
Send CMD0/CMD52 to Card to Reset Card
Write ‘1’ to RSTA Bit to Reset eSDHC
Send 80 Clocks to Card
Voltage Validation
// software reset the host
// get the SDHC_CLK of frequency around 400 KHz
// set the voltage of external card to around 3.0 V
// wait until both bits are cleared
// send 80 clock ticks for card to power-up
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conditions. This means that if the host and
Enhanced Secure Digital Host Controller
20-47