MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 836

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Three-Speed Ethernet Controllers
14.5.3.6.1
Figure 14-55
Table 14-59
14.5.3.6.2
Figure 14-56
Table 14-60
14-88
10–31 TR127 Transmit and receive 65- to 127-byte frame counter—Increments for each good or bad frame transmitted and
10–31
Bits
0–9
Bits
0–9
Offset eTSEC1:0x2_4680;
Reset
Offset eTSEC1:0x2_4684;
Reset
W
W
R
R
Name
Name
TR64 Transmit and receive 64-byte frame counter—Increment for each good or bad frame transmitted and received
eTSEC3:0x2_6680
eTSEC3:0x2_6684
0
0
describes the fields of the TR64 register.
describes the fields of the TR127 register.
describes the definition for the TR64 register.
describes the definition for the TR127 register.
Figure 14-56. Transmit and Receive 65- to 127-Byte Frame Register Definition
Reserved
which is 64 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
Transmit and Receive 64-Byte Frame Counter (TR64)
Transmit and Receive 65- to 127-Byte Frame Counter (TR127)
Reserved
received which is 65–127 bytes in length, inclusive (excluding preamble and SFD but including FCS bytes).
Figure 14-55. Transmit and Receive 64-Byte Frame Register Definition
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-60. TR127 Field Descriptions
Table 14-59. TR64 Field Descriptions
9
9
10
10
All zeros
All zeros
Description
Description
TR64
TR127
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31

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