MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1011

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In basic mode, the channel can be programmed in basic direct mode or basic chaining mode. In extended
mode, the channel can be programmed in extended direct mode or extended chaining mode. Extended
mode provides more capabilities, such as extended descriptor chaining, striding capabilities, and a more
flexible descriptor structure.
The DMA controller supports misaligned transfers for both the source and destination addresses. In order
to maximize performance, the source and destination engines align the source and destination addresses to
a 64-byte boundary. The DMA always reads/writes the maximum number of bytes for a given transfer as
described by the capability inputs of the DMA controller except for globally coherent transactions that use
the size of the cache coherence granule as described by the mode select input.
The DMA controller supports bandwidth control, which prevents a channel from consuming all the data
bandwidth in the controller. Each channel is allowed to consume the bandwidth of the shared resources as
specified by the bandwidth control value. After the channel uses its allotted bandwidth, the arbiter grants
the next channel access to the shared resources. The arbitration is round robin between the channels. This
feature is also used to implement the external control pause feature. If the external control start and pause
are enabled in the MRn, the channel enters a paused state after transferring the data described in the
bandwidth control. External control can restart the channel from a paused state.
The DMA programming model permits software to program each DMA engine independently to interrupt
on completed segment, chain, or error. It also provides the capability for software to resume the DMA
engine from a hardware halted condition by setting the channel continue bit, MRn[CC]. See
for more complete descriptions of the channel states and state transitions.
15.4.1.1
This mode is primarily included for backward compatibility with existing DMA controllers which use a
simple programming model. This is the default mode out of reset. The different modes of operation under
the basic mode are explained in the following sections.
15.4.1.1.1
In basic direct mode, the DMA controller does not read descriptors from memory, but instead uses the
current parameters programmed in the DMA registers to start the DMA transfer. Software is responsible
for initializing SARn, SATRn, DARn, DATRn, and BCRn registers. The DMA transfer is started when
MRn[CS] is set. Software is expected to program all the appropriate registers before setting MRn[CS] to
a 1. The transfer is finished after all the bytes specified in the byte count register have been transferred or
if an error condition occurs. The sequence of events to start and complete a transfer in basic direct mode
is as follows:
Freescale Semiconductor
1. Poll the channel state (see
2. Initialize SARn, SATRn, DARn, DATRn and BCRn.
3. Set the mode register channel transfer mode bit, MRn[CTM], to indicate direct mode. Other control
4. Clear, then set the mode register channel start bit, MRn[CS], to start the DMA transfer.
5. SRn[CB] is set by the DMA controller to indicate the DMA transfer is in progress.
parameters may also be initialized in the mode register.
Basic Direct Mode
Basic DMA Mode Transfer
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
15-23), to confirm that the specific DMA channel is idle.
Table 15-23
DMA Controller
15-25