MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1194

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Transaction
Transaction
Data Link
Data Link
Physical
Physical
Logical Sub-block
Logical Sub-block
Electrical Sub-block
Electrical Sub-block
RX
TX
RX
TX
Figure 17-123. PCI Express High-Level Layering
Packets are formed in the transaction layer (TLPs) and data link layer (DLLPs), and each subsequent layer
adds the necessary encodings and framing—as shown in
Figure
17-124. As packets are received, they are
decoded and processed by the same layers but in reverse order, so they may be processed by the layer or
by the device application software.
Sequence
Framing
Header
Data
ECRC
LCRC
Framing
Number
Transaction Layer
Data Link Layer
Physical Layer
Figure 17-124. PCI Express Packet Flow
17.4.1
Architecture
This section describes implementation details of the PCI Express controller.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
17-98
Freescale Semiconductor