MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 94

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table
Number
14-152
14-153
14-154
14-155
14-156
14-157
14-158
14-159
14-160
14-161
14-162
14-163
14-164
14-165
14-166
14-167
14-168
14-169
14-170
14-171
14-172
14-173
14-174
14-175
14-176
14-177
14-178
14-179
14-180
14-181
14-182
14-183
14-184
14-185
14-186
14-187
14-188
14-189
14-190
14-191
14-192
xciv
8-Bit FIFO Interface Mode Signal Configurations ........................................................... 14-232
Flow Control Frame Structure .......................................................................................... 14-170
Non-Error Transmit Interrupts .......................................................................................... 14-172
Non-Error Receive Interrupts............................................................................................ 14-172
Interrupt Coalescing Timing Threshold Ranges ............................................................... 14-173
Transmission Errors .......................................................................................................... 14-175
Reception Errors ............................................................................................................... 14-175
Tx Frame Control Block Description................................................................................ 14-178
Rx Frame Control Block Descriptions.............................................................................. 14-180
Supported Stack L2 Ethernet Headers .............................................................................. 14-182
Special Filer Rules ............................................................................................................ 14-186
Receive Queue Filer Interrupt Events ............................................................................... 14-186
Filer Table Example—802.1p Priority Filing ................................................................... 14-187
Filer Table Example—IP Diff-Serv Code Points Filing ................................................... 14-188
Filer Table Example—TCP and UDP Port Filing............................................................. 14-189
PTP Payload Special Fields............................................................................................... 14-196
Time-Stamp Insertion Programming Requirements ......................................................... 14-197
Tx Frame Control Block Description................................................................................ 14-199
Transmit Data Buffer Descriptor (TxBD) Field Descriptions .......................................... 14-203
Receive Buffer Descriptor Field Descriptions .................................................................. 14-206
MII Interface Mode Signal Configuration ........................................................................ 14-208
Shared MII Signals............................................................................................................ 14-209
MII Mode Register Initialization Steps............................................................................. 14-209
GMII Interface Mode Signal Configuration ..................................................................... 14-212
Shared GMII Signals......................................................................................................... 14-213
GMII Mode Register Initialization Steps.......................................................................... 14-213
TBI Interface Mode Signal Configuration ........................................................................ 14-216
Shared TBI Signals ........................................................................................................... 14-217
TBI Mode Register Initialization Steps............................................................................. 14-217
RGMII Interface Mode Signal Configuration................................................................... 14-220
Shared RGMII Signals ...................................................................................................... 14-221
RGMII Mode Register Initialization Steps ....................................................................... 14-221
RMII Interface Mode Signal Configuration...................................................................... 14-224
Shared RMII Signals ......................................................................................................... 14-225
RMII Mode Register Initialization Steps .......................................................................... 14-225
RTBI Interface Mode Signal Configuration...................................................................... 14-228
Shared RTBI Signals ......................................................................................................... 14-229
RTBI Mode Register Initialization Steps .......................................................................... 14-229
8-Bit FIFO Mode Register Initialization Steps ................................................................. 14-233
SGMII Interface Signal Configuration (4-Wire)............................................................... 14-234
SGMII Mode Register Initialization Steps........................................................................ 14-234
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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