MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 208

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
Configuration Words Section
The configuration words section is comprised of Config Address and Config Data pairs of adjacent 32-bit
fields. These are typically used to configure the local access windows and the target memory controller’s
registers. They are therefore system-dependent, as they need to be aware of the type and configuration of
memory in a particular system.
The Config Address field has two modes that are selected by the least significant bit in the field (CNT). If
the CNT bit is clear, then the 30 most significant bits are used to form the address pointer and the Config
Data contains the data to be written to this address. If the CNT bit is set then the 30 most significant bits
are used for control instruction. This flexible structure allows the user to configure any 4-byte aligned
memory mapped register, perform control instructions, and specify the end of the configuration stage.
Note that it is illegal to change the content of the CCSRBAR by using this mechanism. Any attempt to do
so will cause the boot process to hang.
The upper 4 most-significant address bits of the 36-bit address are always zero. Consequently the
configuration words can only access memory in the lowest 4 GByte segment of memory. However, since
by default CCSRBAR maps all memory mapped registers within the lowest 4 GByte segment of memory,
and the user is prohibited from changing CCSRBAR with a configuration access, this is not an issue.
4-38
0x80 + 8*(N–1)
0x6C–0x7F
0x8C–0x8F
0x60–0x63
0x64–0x67
0x68–0x6B
0x80–0x83
0x84–0x87
0x88–0x8B
8*(N–1)+4
Address
0x80 +
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Execution Starting Address. Contains the jump address in the system’s local memory address
space into the user’s code first instruction to be executed. This is a 32-bit effective address. The
core is configured in such a way that the 36-bit real address is equal to this (with 4 most significant
bits zero).
Reserved
N. Number of Config Address/Data pairs.
Must be <=1024 (but is recommended to be as small as possible).
Reserved.
Config Address 1
Config Data 1
Config Address 2
Config Data 2
Config Address N
Config Data N (Final Config Data N optional)
User’s Code
Table 4-38. eSPI EEPROM Data Structure (continued)
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Data Bits [0:31]
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