MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 637

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.4
The communication channel provides a full-duplex asynchronous receiver and transmitter using an
operating frequency derived from the platform clock signal.
The transmitter accepts parallel data with a write access to the transmitter holding register (UTHR). In
FIFO mode, the data is placed directly into an internal transmitter shift register, or into the transmitter
FIFO—see
by inserting the appropriate START, STOP, and optional parity bits. Finally, the registers output a
composite serial data stream on the channel transmitter serial data output (SOUT). The transmitter status
may be polled or interrupt-driven.
The receiver accepts serial data on the channel receiver serial data input (SIN), converts the data into
parallel format, and checks for START, STOP, and parity bits. In FIFO mode, the receiver removes the
START, STOP, and parity bits and then transfers the assembled character from the receiver buffer, or
receiver FIFO. This transfer occurs in response to a read of the UART receiver buffer register (URBR).
The receiver status may be polled or interrupt driven.
12.4.1
The UART bus is a serial, full-duplex, point-to-point bus as shown in
devices are attached to the same signals and there is no need for address or arbitration bus cycles.
Freescale Semiconductor
DMS
0
0
1
1
SOUT1
rxcnt
START
FEN
0
1
0
1
Functional Description
Section 12.4.5, “FIFO Mode.”
Serial Interface
D6 D5 D4 D3 D2 D1 D0 PTY
1
DMA Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
0
0
0
1
Figure 12-16. UART Bus Interface Transaction Protocol Example
3
Data Bits
Two 7-bit data transmissions with parity and 2-bit STOP transactions
RXRDY is cleared when there is at least one character in the receiver FIFO or URBR.
RXRDY is cleared when the trigger level or a time-out has been reached. RXRDY remains
cleared until the receiver FIFO is empty.
4
Table 12-23. UDSR[RXRDY] Cleared Conditions
5
6
Even/Odd Parity
7
Optional
The transmitting registers convert the data to a serial bit stream,
8
STOP Bits
9
10
START
D6 D5 D4 D3 D2 D1 D0 PTY
1
Meaning
2
3
Figure
Data Bits
4
5
12-16. Therefore, only two
6
7
Optional
Even/Odd Parity
8
STOP Bits
9
10
DUART
12-19