MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 154

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions
TSEC3_GTX_CLK TSEC3 transmit clock out
3-4
TSEC_1588_CLK
TSEC1_RXD[7:0]
TSEC3_TXD[6:4]
TSEC3_TXD[1:0]
TSEC3_RXD[7:0]
TSEC1_RX_CLK
TSEC3_RX_CLK
TSEC3_TX_CLK
TSEC1_RX_ER
TSEC3_RX_ER
TSEC1_RX_DV
TSEC3_TX_EN
TSEC3_TX_ER
TSEC3_RX_DV
TRIG_OUT[0:1]
PULSE_OUT1
PULSE_OUT2
TSEC3_TXD7
TSEC3_TXD3
TSEC3_TXD2
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC3_CRS
TRIG_IN[0:1]
TSEC1_COL
TSEC3_COL
CLK_OUT
LAD[0:31]
LDP[0:3]
Name
Table 3-1. MPC8536E Signal Reference by Functional Block (continued)
TSEC1 collision detect
TSEC1 receive data
TSEC1 receive data valid
TSEC1 receiver error
TSEC1 receive clock
TSEC3 transmit data 7
TSEC3 transmit data [6:4]
TSEC3 transmit data 3
TSEC3 transmit data 2
TSEC3 transmit data 1–0
TSEC3 transmit enable
TSEC3 transmit error
TSEC3 transmit clock in
TSEC3 carrier sense
TSEC3 collision detect
TSEC3 receive data 7–0
TSEC3 receive data valid
TSEC3 receive error
TSEC3 receive clock
IEEE 1588 clock
IEEE 1588 clock out
IEEE 1588 trigger in
IEEE 1588 pulse out 1
IEEE 1588 pulse out 2
IEEE 1588 alarm out
Local bus address/data
Local bus data parity
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
Functional
IEEE 1588
IEEE 1588
IEEE 1588
IEEE 1588
IEEE 1588
IEEE 1588
eTSEC1
eTSEC1
eTSEC1
eTSEC1
eTSEC1
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
eTSEC3
Block
eLBC
eLBC
Alternate Function(s)
cfg_tsec3_prtcl[1:0]
cfg_srds2_ref_clk0
cfg_srds2_ref_clk1
cfg_tsec3_reduce
FIFO3_TXD[6:4]/
FIFO3_TXD[1:0]/
cfg_gpinput[0:31]
FIFO1_RXD[7:0]
cfg_io_ports[0:2]
FIFO3_RXD[7:0]
cfg_srds2_prtcl1
cfg_srds2_prtcl2
FIFO1_RX_CLK
FIFO3_TX_CLK
FIFO3_RX_CLK
FIFO3_TX_ER/
cfg_ddr_pll[0:1]
FIFO1_RX_DV
FIFO1_RX_ER
FIFO3_RX_FC
FIFO3_RX_DV
FIFO3_RX_ER
FIFO1_TX_FC
FIFO3_TX_EN
FIFO3_TX_FC
cfg_eng_use2
FIFO3_TXD7/
FIFO3_TXD3/
FIFO3_TXD2/
cfg_ddr_pll2
—
—
—
Signals
No. of
32
1
8
1
1
1
1
3
1
1
2
1
1
1
1
1
1
8
1
1
1
1
1
2
1
1
2
4
Freescale Semiconductor
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
14-2/14-10
13-2/13-5
13-2/13-5
Table/
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