MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 479

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Channel 1 always has the highest priority, but cannot make back-to-back requests. It follows that the
second highest priority channel wins arbitration either immediately, or after one win for channel 1.
Note that the SEC does not dynamically adjust its own transaction priorities. System software, however,
can adjust SEC transaction priority in real time, with the change in priority taking effect immediately.
10.5.3
10.5.3.1
All interrupt outputs from other SEC blocks are fed to the controller as interrupt conditions. In addition,
the controller itself detects some interrupt conditions. The controller maintains an interrupt status register
(ISR) with bits corresponding to all of these possible interrupt conditions. If an interrupt condition occurs
and the corresponding bit of the interrupt enable register (IER) is set, then the associated ISR bit is set,
indicating the presence of a pending interrupt.
A channel can generate frequent interrupts, especially if it is configured to interrupt at the completion of
each descriptor. To make sure that the host receives the right number of interrupts, each channel done
interrupt has a special “queuing” feature. If multiple channel done interrupts are generated before the first
is cleared, then the additional interrupts are counted by the controller. Each time the host clears a channel
interrupt, the count is decremented. If the host clears the channel interrupt and the count reaches zero, the
channel done interrupt is negated. If the count does not reach zero, the controller negates the interrupt for
one cycle and then re-asserts it.
Up to 15 interrupts can be queued for each channel. If the count of queued interrupts for any channel
exceeds 15, then that channel’s done overflow bit is set in the channel’s ISR (if the corresponding IER bit
is set), and the channel done interrupt is asserted.
10.5.3.2
Interrupt conditions from the channels and controller can only be blocked through the controller’s IER, as
described in Section 10.5.3.1. However, the EU interrupt conditions may be blocked at two different
levels. There is an interrupt mask register in each EU which can block particular interrupt conditions
before they reach the EU’s interrupt status register. In addition, interrupts from EUs can be individually
blocked by bits of the controller’s IER before they reach the controller’s ISR. For normal operation,
interrupts from EUs are typically disabled in the controller’s IER, but they still reach the channel, and the
channel produces done or error interrupts to the host as needed.
10.5.3.3
To handle an interrupt, the host must read the ISR to determine the source. If necessary, the host may read
the interrupt status registers of other blocks to ascertain the cause. In some cases, the host may need to take
action to clear the root cause of the interrupt. Once the appropriate action is taken, the host can clear the
ISR bit by setting the corresponding bit of the interrupt clear register (ICR). If the cause of the interrupt
condition has not been cleared, or if there is another interrupt condition from the same source, then the ISR
bit clears for a cycle and then goes high again, and the interrupt signal to the host remains high. If the ISR
Freescale Semiconductor
Controller Interrupts
Controller Interrupt Conditions and Interrupt Generation
Blocking of Interrupts
Interrupt Handling
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Security Engine (SEC) 3.0
10-49