MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 223

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SRAM features include the following:
Table 6-1
Freescale Semiconductor
•
•
•
•
•
Error injection modes supported for testing error handling
SRAM regions are created by configuring 1, 2, 4 or 8 ways of each set to be reserved for
memory-mapped SRAM.
Regions can reside at any location in the memory map aligned to the SRAM size.
SRAM memory is byte addressable; for accesses of less than a cache line, ECC is updated using
read-modify-write transactions.
I/O devices access SRAM regions by marking transactions as snoopable (global).
lists the possible L2 cache/SRAM configurations.
512 Kbytes (8 ways)
448 Kbytes (7 ways)
384 Kbytes (6 ways)
320 Kbytes (5 ways)
256 Kbytes (4 ways)
192 Kbytes (3 ways)
128 Kbytes (2 ways)
Cache
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Table 6-1. Available L2 Cache/SRAM Configurations
Stash-only Region
128 Kbytes
128 Kbytes
128 Kbytes
256 Kbytes
256 Kbytes
128 Kbytes
256 Kbytes
256 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
—
—
—
—
—
SRAM Region 1
128 Kbytes
128 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
256 Kbytes
128 Kbytes
256 Kbytes
128 Kbytes
128 Kbytes
512 Kbytes
256 Kbytes
256 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
—
—
—
—
SRAM Region 2
128 Kbytes
128 Kbytes
128 Kbytes
256 Kbytes
128 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L2 Look-Aside Cache/SRAM
6-3