MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 549

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.5.2
The KEU key size register, shown in
to 16 bytes. This register is cleared when the KEU is reset or re-initialized. If a key size is specified that
does not match the selected algorithm(s), an illegal key size error is generated.
Freescale Semiconductor
62–63
Bits
57
58
59
60
61
Reset
Field
Addr
EDGE Select EDGE A5/3 blocks
R/W
Name
CICV Compare integrity check values.
ALG
INT
PE
—
KEU Key Size Register (KEUKSR)
0
0 Normal operation; no ICV comparison.
1 After the ICV is computed, compare it to the data in the KEU’s ICV_In register. If the ICVs do not match, send
0 EDGE A5/3 blocks not selected
1 EDGE A5/3 blocks selected
Note 1: For EDGE A5/3, two 348-bit blocks are required to be produced each 4.615mS slot. If EDGE = 1, the
Note 2: If EDGE = 0, 696 contiguous bits may be read with successive reads of the output FIFO. In this case
Note 3: If EDGE is set to 1, whilst GSM = 1, an interrupt/error is generated.
Process end of message. Enables final processing of last message block (f9 only).
0 Prevent final block processing (message incomplete)
1 Enable final block processing (message complete)
Note: PE is closely connected with the KEU data size register, see
Initialization. Enables initialization for a new message.
0 Prevent initialization
1 Enable initialization
Note: For f8 or f9 operations, if the 3G frame (or message) is being processed through a single descriptor, the
Reserved
Algorithm selection. Specifies the functions to perform.
00 Perform f8 function only
01 Reserved
10 Perform f9 function only
11 Reserved
an error interrupt to the channel. Only applicable when the ALG field is set to a function that uses f9.
first five reads of the output FIFO retrieve the first 320 bits of block 1. The sixth read of the output FIFO
retrieves the final 28 bits of block 1 (the remaining bits of the sixth 64-bit word are cleared to zero). The next
five reads of the output FIFO retrieve the first 320 bits of block 2. The following read of the output FIFO
retrieves the final 28 bits of block 2 (the remaining bits of this 64-bit word are cleared to zero).
the host (application) is responsible for handling the A5/3 block formatting.
(KEUDSR)”
Initialization bit should be set. If the frame is split across multiple descriptors, this bit should only be set in
the descriptor that processes the first block of the message.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-53. KEU Mode Register Field Descriptions (continued)
for more details.
Figure 10-65. KEU Key Size Register
Figure
—
10-65, stores the number of bytes in the key. It should be set
KEU 0x3_E008
Description
R/W
0
Section 10.7.5.3, “KEU Data Size Register
51
52
Key Size (Bytes)
Security Engine (SEC) 3.0
63
10-119