MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1682

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

O
P
Glossary-6
OCeaN. (On-chip network) Non-blocking crossbar switch fabric. Enables full duplex port
Outbound ATMU windows. Mappings that perform address translations from local
Packet. A unit of binary data that can be routed through a network. Sometimes packet is
Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory aligned
Page access history bits. The changed and referenced bits in the PTE keep track of the
Page fault. A page fault is a condition that occurs when the processor attempts to access
Page table. A table in memory is comprised of page table entries, or PTEs. It is further
Page table entry (PTE). Data structures containing information used to translate
Physical coding sublayer (PCS). Sublayer responsible for encoding and decoding data
Physical medium attachment (PMA) sublayer. Sublayer responsible for serializing code
Physical medium dependent (PMD) sublayer. Sublayer responsible for signal
MPC83536E PowerQUICC™ III Integrated Processor Reference Manual, Rev. 1
connections at 128Gb/s concurrent throughput and independent per port
transaction queuing and flow control. Permits high bandwidth, high performance,
as well as the execution of multiple data transactions.
32-bit address space to the address spaces of, which may be much larger than the
local space. Outbound ATMU windows also map attributes such as transaction
type or priority level.
used to refer to the frame plus the preamble and start frame delimiter (SFD).
on a 4-Kbyte boundary.
access history within the page. The referenced bit is set by the MMU whenever
the page is accessed for a read or write operation. The changed bit is set when the
page is stored into. See
a memory location that does not reside within a page not currently resident in
physical memory. A page fault exception condition occurs when a matching, valid
page table entry (PTE[V] = 1) cannot be located.
organized into eight PTEs per PTEG (page table entry group). The number of
PTEGs in the page table depends on the size of the page table (as specified in the
SDR1 register).
address
information in a 32-bit processor and 16 bytes of information in a 64-bit processor.
stream to and from the MAC sublayer.
groups into a bit stream suitable for serial bit-oriented physical devices (SERDES)
and vice versa. Synchronization is also performed for proper data decoding in this
sublayer. The PMA sits between the PCS and the PMD sublayers.
transmission. The typical PMD functionality includes amplifier, modulation, and
wave shaping. Different PMD devices may support different media.
to physical address on a 4-Kbyte page basis. A PTE consists of 8 bytes of
Changed bit
and
Referenced
bit.
Freescale Semiconductor
effective