MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 282

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8-8
MCS[0:3]
Signal
MCAS
MRAS
MWE
Table 8-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
I/O
O
O
O
O
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Column address strobe. Active-low SDRAM address multiplexing signal. MCAS is asserted for read or
write transactions and for mode register set, refresh, and precharge commands.
Row address strobe. Active-low SDRAM address multiplexing signal. Asserted for activate commands.
In addition; used for mode register set commands and refresh commands.
Chip selects. Four chip selects supported by the memory controller.
Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode
registers set commands and precharge commands.
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—Assertion and negation timing is directed by the values described in
Timing Assertion/Negation—Assertion and negation timing is directed by the values described in
Timing Assertion/Negation—Asserted to signal any new transaction to the SDRAM. The transaction
Timing Assertion/Negation—Similar timing as MRAS and MCAS. Used for write commands.
State
State
State
State
Asserted—Indicates that a valid SDRAM column address is on the address bus for read and
Negated—The column address is not guaranteed to be valid.
High impedance—MCAS is always driven unless the memory controller is disabled.
Asserted—Indicates that a valid SDRAM row address is on the address bus for read and
Negated—The row address is not guaranteed to be valid.
High impedance—MRAS is always driven unless the memory controller is disabled.
Asserted—Selects a physical SDRAM bank to perform a memory operation as described in
Negated—Indicates no SDRAM action during the current cycle.
High impedance—Always driven unless the memory controller is disabled.
Asserted—Indicates a memory write operation. See
Negated—Indicates a memory read operation.
High impedance—MWE is always driven unless the memory controller is disabled.
write transactions. See
for various other SDRAM commands.
Section 8.4.1.5, “DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),”
Section 8.4.1.6, “DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),”
Section 8.4.1.7, “DDR SDRAM Timing Configuration 2
Section 8.4.1.4, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).”
write transactions. See
for various other SDRAM commands.
Section 8.4.1.5, “DDR SDRAM Timing Configuration 0 (TIMING_CFG_0),”
Section 8.4.1.6, “DDR SDRAM Timing Configuration 1 (TIMING_CFG_1),”
Section 8.4.1.7, “DDR SDRAM Timing Configuration 2
Section 8.4.1.4, “DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).”
Section 8.4.1.1, “Chip Select Memory Bounds (CSn_BNDS),”
“Chip Select Configuration (CSn_CONFIG).”
MCS[0:3] signals to begin a memory cycle.
must adhere to the timing constraints set in TIMING_CFG_0–TIMING_CFG_3.
states required on MWE for various other SDRAM commands.
Table 8-61
Table 8-61
Description
for more information on the states required on MCAS
for more information on the states required on MRAS
The DDR controller asserts one of the
Table 8-61
(TIMING_CFG_2),” and
(TIMING_CFG_2),” and
for more information on the
Freescale Semiconductor
and
Section 8.4.1.2,