MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1324

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.6.3.1.2
The write operation can be paused during the transfer. Instead of stopping the SDHC_CLK at any time to
pause all the operations which is also inaccessible to the host driver, the driver can set
PROCTL[SABGREQ] to pause the transfer between the data blocks. Since there is no timeout condition
in a write operation during the data blocks, a write operation to the cards can be paused in this way and if
line SDHC_DAT0 is not required to de-assert to release busy state, no suspend command is needed.
Similar to the flow described in
the same type of write operations:
The number of blocks left during the data transfer is accessible by reading the content of
BLKATTR[BLKCNT]. Due to the data transfers and setting PROCTL[SABGREQ] are concurrent, along
with the delay of register read and the register setting, the actual number of blocks left may not be the same
as the value read earlier. The driver should read the value of BLKATTR[BLKCNT] after the transfer is
paused and the transfer complete interrupt is received.
It is also possible that the transfer of the last block begins when the stop-at-block-gap request is sent to the
buffer. In this case, the next block gap is the actual end of the transfer, and therefore, the request is ignored.
The driver should treat this as a non-pause transfer and a common write operation.
When the write operation is paused, the data transfer inside the host system does not stop and the transfer
remains active until the data buffer is full. The eSDHC reads the resume command as a normal command
with a data transfer, and it is the driver’s responsibility to set all the relevant registers before the transfer
is resumed. If there is only one block to send when the transfer is resumed, XFERTYP[MSBSEL, BCEN,
AC12EN] are set. However, the eSDHC automatically sends CMD12 to mark the end of multi-block
transfer.
20-50
1. Check the card status and wait until card is ready for data.
2. Set the card block length.
3. Set the eSDHC BLKATTR[BLKSIZE] to the same as the block length set in the card in step 2.
4. Set eSDHC BLKATTR[BLKCNT] with the number of blocks to send.
5. Disable the buffer write ready interrupt, configure the DMA setting, and enable the eSDHC DMA
6. Set PROCTL[SABGREQ].
7. Wait for the transfer complete interrupt.
8. Clear PROCTL[SABGREQ].
9. Check the status bit to see if a read CRC error occurred.
10. Set PROCTL[CREQ] to continue the read operation.
11. Wait for the transfer complete interrupt.
12. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
— MMC/SD cards — use SET_BLOCKLEN (CMD16)
when sending the command with data transfer. Set XFERTYP[AC12EN].
CMD12 and receiving the response.
Write with Pause
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 20.6.3.1.1, “Normal Write,”
the write with pause is shown with
Freescale Semiconductor