MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1135

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.6.6.2
PEX_ERR_CAP_R1 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
Table 17-30
in PEX_ERR_CAP_R0 (see
transaction.
Freescale Semiconductor
Offset 0xE2C
Reset
W
R
0
24–31
0–23
0–31
Bits
Bits
describes the fields of PEX_ERR_CAP_R1 for the case when the FMT and TYPE subfields
PEX_ERR_CAP_R1—Inbound Case
Figure 17-31. PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
Table 17-29. PCI Express Error Capture Register 1 Field Descriptions
Table 17-30. PCI Express Error Capture Register 1 Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Name
OD0
GH1
—
Reserved
Internal platform transaction information. Reserved for factory debug.
PEX second DW (4-byte) header. This field contains the second DW (4-byte) of the
captured PCI Express packet header.
24–31
16–23
12–15
11
8–10
0–7
External Source, Inbound CompletionTransaction
Table
Internal Source, Outbound Transaction
External Source, Inbound Transaction
17-28) indicate the error was caused by an inbound completion
Comp ID[15:8]
Comp ID[7:0]
Byte Count[11:8]
BCM
Comp Status
Byte Count[7:0]
All zeros
GH1
Description
Description
PCI Express Interface Controller
Figure
Access: Read/Write
17-31.
17-39
31