MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1046

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Section 16.3.2.11, “PCI Base Address Registers.”
byte lane redirection from the little-endian PCI bus to the big-endian CCSRBAR configuration space.
16.3.1.3.1
The PCI inbound translation address registers (PITARn) points to the beginning of the local address space
for the inbound window. The translated address is created by concatenating the transaction offset to this
translation address. The format of the PITARn is shown in
Table 16-11
16.3.1.3.2
The PCI inbound window base address registers (PIWBARn) select the PCI base address for the windows
that are translated to the internal platform address space. Addresses for inbound transactions are compared
to these windows. If a PCI transaction does not fall within one of these spaces, then the PCI interface does
not assert DEVSEL. The PIWBARn is shown in
Table 16-12
16-20
Offset 0xDA0, 0xDC0, 0xDE0
Offset 0xDA8, 0xDC8, 0xDE8
Reset
Reset
12–31
W
W
0–11
R
Bits Name
R
0
0
TEA Translation extended address. Bits 0–7 are reserved; bits 8–11 correspond to bits [0:3] of the local
TA
describes the fields of the PITARn registers
describes the fields of the PIWBARn registers.
PCI Inbound Translation Address Registers (PITAR n )
PCI Inbound Window Base Address Registers (PIWBAR n )
translation address.
0x000 – 0x00F are valid.
0x010 and greater are reserved.
Translation address. Indicates the starting point of the inbound translated address. The specified
address must be aligned to the window size, as defined by PIWAR n [IWS]. TA corresponds to bits [4:23]
of the 36-bit local translation address.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 16-11. PCI Inbound Translation Address Registers (PITAR n )
Figure 16-12. PCI Inbound Window Base Address Registers
BEA
TEA
Table 16-11. PITAR n Field Descriptions
11 12
11 12
Figure
All accesses to PCSRBAR have an automatic internal
All zeros
All zeros
Description
16-12.
Figure
16-11.
BA
TA
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31