MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 265

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2
Table 7-1
are reserved.
In this table and in the register figures and field descriptions, the following access definitions apply:
7.2.1
This section consists of detailed descriptions of those registers summarized in
registers are shown in big-endian format.
7.2.1.1
The ECM CCB address configuration register, shown in
policies for the CCB.
Freescale Semiconductor
Offset 0x0_1000
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Local Memory Offset
W
•
•
•
•
•
R
0
0x0_1BFC
0x0_1E0C
0x0_1BF8
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
0x0_1000
0x0_1010
0x0_1E00
0x0_1E08
0x0_1E10
0x0_1E14
shows the ECM’s memory map. Undefined 4-byte address spaces within offset 0x000–0xFFF
Memory Map/Register Definition
Register Descriptions
ECM CCB Address Configuration Register (EEBACR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 7-2. ECM CCB Address Configuration Register (EEBACR)
EEBACR—ECM CCB address configuration register
EEBPCR—ECM CCB port configuration register
ECM IP Block Revision Register 1
ECM IP Block Revision Register 2
EEDR—ECM error detect register
EEER—ECM error enable register
EEATR—ECM error attributes capture register
EELADR—ECM error low address capture register
EEHADR—ECM error high address capture register
—
Table 7-1. ECM Memory Map
Register
Figure
27
A_STRM_DIS CORE_STRM_DIS A_STRM_CNT
7-2, controls arbitration and streaming
Access
28
0
R/W
R/W
R/W
w1c
R
R
R
R
R
0x0000_0003
0x0 n 00_0000
0x0001_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Table
Reset
29
0
7-1. Note that these
e500 Coherency Module
Access: Read/Write
Section/page
7.2.1.1/7-3
7.2.1.2/7-4
7.2.1.3/7-5
7.2.1.4/7-5
7.2.1.5/7-6
7.2.1.6/7-7
7.2.1.7/7-7
7.2.1.8/7-8
7.2.1.9/7-9
30
1
31
1
7-3