MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 778

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-30
17–19
25–26
Bits
11
12
13
14
15
16
20
21
22
23
24
MMWR MII management write completion
MMRD
GRSC
Name
XFUN
MAG
RXB
CRL
RXF
TXF
LC
—
—
—
transmit buffer descriptor (TxBD) was updated. This only occurs if the I (interrupt) bit in the status word of
the buffer descriptor is set. The specific transmit queue that was updated has its TXF bit set in TSTAT.
0 No frame transmitted/TxBD not updated.
1 Frame transmitted/TxBD updated.
Reserved
Late collision. This bit indicates that a collision occurred beyond the collision window (slot time) in
half-duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.
0 No late collision occurred.
1 Late collision occurred.
the MAC’s half-duplex register’s retransmission maximum count (HAFDUP[Retransmission Maximum]). The
frame is discarded without being transmitted and the queue halts (TSTAT[THLT n ] set to 1). This only occurs
while in half-duplex mode.
0 Successive transmission collisions do not exceed maximum.
1 Successive transmission collisions exceed maximum.
was transmitted.
0 Transmit FIFO not underrun.
1 Transmit FIFO underrun.
set in its status word and was not the last buffer descriptor of the frame.
0 Receive buffer descriptor not updated.
1 Receiver buffer descriptor updated.
Reserved
Magic Packet detected when the eTSEC is in Magic Packet detection mode (MACCFG2[MPEN] = 1).
0 No Magic Packet received, or Magic Packet mode was not enabled.
1 A Magic Packet was received while in Magic Packet mode. MACCFG2[MPEN] is also cleared upon
MII management read completion
0 MII management read not issued or in process.
1 MII management read completed that was initiated by a user through the MII Scan or Read cycle
0 MII management write not issued or in process.
1 MII management write completed that was initiated by a user write to the MIIMCON register.
the user to know if the system has completed the stop and it is safe to write to receive registers (status,
control or configuration registers) that are used by the system during normal operation.
0 Graceful stop not completed.
1 Graceful stop completed.
(RxBD) in that frame was updated. This occurs either if the I (interrupt) bit in the buffer descriptor status word
is set, or an overrun error occurs. The specific receive queue that was updated has its RXF bit set in RSTAT.
0 Frame not received.
1 Frame received.
Reserved
Transmit frame interrupt. This bit indicates that a frame was transmitted and that the last corresponding
Collision retry limit. This bit indicates that the number of successive transmission collisions has exceeded
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame
Receive buffer. This bit indicates that a receive buffer descriptor was updated which had the I (Interrupt) bit
Graceful receive stop complete. This interrupt is asserted if a graceful receive stop is completed. It allows
Receive frame interrupt. This bit indicates that a frame was received and the last receive buffer descriptor
receiving the Magic Packet.
command.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-8. IEVENT Field Descriptions (continued)
Description
Freescale Semiconductor