MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1389

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
7–0
Status
Name
This field is used by the host controller to communicate individual command execution states back to the
host controller driver (HCD) software. This field contains the status of the last transaction performed on this
qTD. The bit encodings are:
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Bits
7
6
5
4
3
2
1
0
Table 21-53. qTD Token (DWord 2) (continued)
Active. Set by software to enable the execution of transactions by the host controller.
Halted. Set by the host controller during status updates to indicate that a serious error
has occurred at the device/endpoint addressed by this qTD. This can be caused by
babble, the error counter counting down to zero, or reception of the STALL handshake
from the device during a transaction. Any time that a transaction results in the Halted
bit being set, the Active bit is also cleared.
Data buffer error. Set by the host controller during status update to indicate that the
host controller is unable to keep up with the reception of incoming data (overrun) or is
unable to supply data fast enough during transmission (under run). If an overrun
condition occurs, the host controller will force a time-out condition on the USB,
invalidating the transaction at the source. If the host controller sets this bit to a one, then
it remains a one for the duration of the transfer.
Babble detected. Set by the host controller during status update when babble is
detected during the transaction. In addition to setting this bit, the host controller also
sets the Halted bit to a one. Since babble is considered a fatal error for the transfer,
setting the Halted bit to a one insures that no more transactions occur because of this
descriptor.
Transaction error (XactErr). Set by the host controller during status update in the case
where the host did not receive a valid response from the device (time-out, CRC, bad
PID). If the host controller sets this bit to a one, then it remains a one for the duration
of the transfer.
Missed micro-frame. This bit is ignored unless the QH[EPS] field indicates a full- or
low-speed endpoint and the queue head is in the periodic list. This bit is set when the
host controller detected that a host-induced hold-off caused the host controller to miss
a required complete-split transaction. If the host controller sets this bit to a one, then it
remains a one for the duration of the transfer.
Split transaction state (SplitXstate). This bit is ignored by the host controller unless the
QH[EPS] field indicates a full- or low-speed endpoint. When a full- or low-speed device,
the host controller uses this bit to track the state of the split- transaction. The functional
requirements of the host controller for managing this state bit and the split transaction
protocol depends on whether the endpoint is in the periodic or asynchronous schedule.
The bit encodings are:
0 Do start split. This value directs the host controller to issue a start split transaction
1 Do complete split. This value directs the host controller to issue a Complete split
Ping state (P)/ERR. If the QH[EPS] field indicates a high-speed device and the PID
Code indicates an OUT endpoint, then this is the state bit for the Ping protocol. The bit
encodings are:
0 Do OUT. This value directs the host controller to issue an OUT PID to the endpoint.
1 Do Ping. This value directs the host controller to issue a PING PID to the endpoint.
If the QH[EPS] field does not indicate a high-speed device, then this field is used as an
error indicator bit. It is set by the host controller whenever a periodic split-transaction
receives an ERR handshake.
to the endpoint.
transaction to the endpoint.
Description
Status Field Description
Universal Serial Bus Interfaces
21-55