MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 240

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
6.3.1.4.2
The error control and capture registers control detection and reporting of tag parity, ECC and L2
configuration errors. L2 configuration errors are illegal combinations of L2 size and block size and are
detected when the L2 is enabled (L2CTL[L2E] = 1).
register (L2CAPTDATAHI).
Table 6-13
Figure 6-17
Table 6-14
Figure 6-18
6-20
Offset 0x2_0E20
Offset 0x2_0E24
Offset 0x2_0E28
Reset
Reset
Reset
W
W
W
R
R
R
0
0
0
describes L2CAPTDATAHI[L2DATA].
describes L2CAPTDATALO[L2DATA].
shows the L2 error capture data low register (L2CAPTDATALO).
shows the L2 error syndrome register (L2CAPTECC).
ECCSYND
Error Control and Capture Registers
Figure 6-17. L2 Error Capture Data Low Register (L2CAPTDATALO)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 6-16. L2 Error Capture Data High Register (L2CAPTDATAHI)
Figure 6-18. L2 Error Syndrome Register (L2CAPTECC)
0–31
0–31
Bits
Bits
7
Table 6-14. L2CAPTDATALO Field Description
Table 6-13. L2CAPTDATAHI Field Description
8
L2DATA
L2DATA
Name
Name
L2 data high word
L2 data low word
All zeros
All zeros
All zeros
L2DATA
L2DATA
Figure 6-16
—
Description
Description
shows the L2 error capture data high
23 24
Freescale Semiconductor
ECCCHKSUM
Access: Read Only
Access: Read Only
Access: Read Only
31
31
31