MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1314

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20.5.2
The internal DMA implements a DMA engine and CCB master. When the internal DMA is enabled
(XFERTYP[DMAEN] is set), the buffer interrupt status bits are still set if they are enabled. To avoid
setting them, clear IRQSTATEN[BWRSEN, BRRSEN]. See
CCB interface block. The internal DMA must not be used to read (or write) data if the data will be written
(or read) by the CPU or an external DMA through the DATPORT register.
20.5.2.1
If the watermark level is met in the data transfer and the internal DMA is enabled, the data buffer block
sends a DMA request to this block. Meanwhile, the external DMA request is disabled. The delay of
response from the internal DMA engine depends on the system bus loading and the priority assigned to
eSDHC. The DMA engine does not respond to the request during its burst transfer, and is available as soon
as the burst is over. The data buffer deasserts the request once an access on the buffer is made. Upon access
to the buffer by the internal DMA, the data buffer updates its internal buffer pointer and when the
watermark level is satisfied, another DMA request is sent.
The data transfer is in the block unit and the last watermark level is always set to the remaining number of
words. For instance, for a multi-block data read with each block size of 31 bytes, the burst length is set at
six words. After the first burst transfer, if there are more than seven bytes in the buffer, which might be
partly some data of the next block, another DMA read request is sent because the remaining number of
words to send for the current block is (31 – 6 4) 4 = 2, and eSDHC reads two words out of the buffer,
with seven valid bytes and one stuff byte automatically added by eSDHC.
20.5.2.2
Just like the CPU polling access, the DMA burst length for the internal DMA engine does not a restriction
other than the maximum size. The burst length for read or write can be 1–128 words. The actual burst
length for the DMA depends on which is smaller: configured watermark level or the remaining words of
current block.
Take the example in
length is two words to complete the 31-byte block. The burst length then changes back to six words to
prepare for the next 31-byte block. The host driver writer may take this variable burst length into account.
20-40
DMA CCB Interface
Internal
DMA Burst Length
Cluster
Signal
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
CCB
Section 20.5.2.1, “Internal DMA Request,”
DMA Request
Figure 20-22. DMA CCB Interface Block
Interface
Engine
Master
Logic
DMA
CCB
System Address
Error Indication
Data Exchange
R/W Indication
DMA Request
Burst Length
Figure 20-22
again. After six words are read, the burst
eSDHC Registers
for illustration of the DMA
Buffer Control
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