MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 536

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.3.10 CRCU ICV Size Register
The CRCU ICV size register (shown in
MDEU. Values written to this location are always ignored, and reads from this location always returns
zero. A context error is generated if this register is written after processing has begun.
10.7.3.11 CRCU End of Message Register
The CRCU end of message register (shown in
written to the CRCU (in channel-driven access, this signaling is done automatically). A write to this
register is required to complete a CRC32 operation. The CRCU starts processing message data as soon as
the data size register is written and data becomes available in the FIFO, but it does not process a remaining
partial word or perform an ICV check until this register is written.
Any value written to this register has the same effect. Reading this register returns a zero value.
10.7.3.12 CRCU Context Register
This register can be written with an intermediate CRC result or desired initial state prior to processing any
data. Once processing is complete, the CRC result is available from this register. Note that the CRC result
is stored in the upper half of this register; the lower half is not used. The reset state of this register is all
ones, as this allows the CRC32 algorithm to detect bit errors in the leading zeros of a message.
Figure 10-50
if this register is written after processing has begun. An early read error is generated if this register is read
while the module is busy.
10-106
Offset 0x3_F050
Reset
W
R
Reset
0
Field
Addr
R/W
shows the bit position of each term in the written context value. A context error is generated
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-49. CRCU End of Message Register
Figure 10-48. CRCU ICV Size Register
Figure
10-48) is word readable/writable for compatibility with the
Figure
CRCU 0x3_F040
All zeros
10-49) is used to indicate that all data has been
R/W
—
0
Freescale Semiconductor
Access: Write only
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