MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1427

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 21-55
each split transaction. The first is a single start-split transaction, which occurs when the SplitXState is at
Do_Start and the single bit in cMicroFrameBit has a corresponding bit active in QH[S-mask]. The
transaction translator does not acknowledge the receipt of the periodic start-split, so the host controller
unconditionally transitions the state to Do_Complete. Due to the available jitter in the transaction
translator pipeline, there will be more than one complete-split transaction scheduled by software for the
Do_Complete state. This translates simply to the fact that there are multiple bits set in the QH[C-mask]
field.
The host controller keeps the queue head in the Do_Complete state until the split transaction is complete
(see definition below), or an error condition triggers the three-strikes-rule (for example, after the host tries
the same transaction three times, and each encounters an error, the host controller stops retrying the bus
transaction and halts the endpoint, thus requiring system software to detect the condition and perform
system-dependent recovery).
21.6.12.2.6 Periodic Interrupt—Do-Start-Split
This is the state software must initialize a full- or low-speed interrupt queue head StartXState bit. This state
is entered from the Do_Complete Split state only after the split transaction is complete. This occurs when
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corresponds to the current micro-frame number. For example, if the current micro-frame is 0, then
cMicroFrameBit will equal 0b0000_0001.
The variable cMicroFrameBit is used to compare against the S-mask and C-mask fields to
determine whether the queue head is marked for a start- or complete-split transaction for the
current micro-frame.
CERR –– > 0
Data Loss
Babble
STALL
.or.
.or.
.or.
illustrates how a complete interrupt split transaction is managed. There are two phases to
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Queue
State
Figure 21-55. Split Transaction State Machine for Interrupt
Halt
Queue
Active
State
Transaction
Complete
MDATA
NYET
Split
.or.
cMicroFrameBit)
!(QH.S-Mask &
Complete-
Start-
Split
Split
Do
Do
XactErr
cMicroFrameBit)
(QH.S-Mask &
* Issue Start-Split Transaction
* Tag QH with Frame Number According
* QH.C-prog-mask = zero(0x00)
to the Frame Tag Rules **(1,3)
Decrement Error Counter (CERR)
* Issue Complete-Split Transaction
* Tag QH with Frame Number According
* C-prog-mask |= cMicroFrameBit
to the **Sframe Tag Rules
and Do Immediate Retry
of Complete-Split
CheckPreviousBit(QH.C-prog-mask,
(FRINDEX[7
(QH.C-Mask & cMicroFrameBit)
QH.C-Mask, cMicroFrameBit)
–
3] .eq. QH.FrameTag)
.and.
.and.
Universal Serial Bus Interfaces
21-93