MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 181

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3
Various device functions are initialized by sampling certain signals during the assertion of HRESET. The
values of all these signals are sampled into registers while HRESET is asserted. These inputs are to be
pulled high or low by external resistors. During HRESET, all other signal drivers connected to these
signals must be in the high-impedance state.
Most POR configuration signals have internal pull-up resistors so that if the desired setting is high, there
is no need for a pull-up resistor on the board. Other POR configuration signals do not use pull-ups and
therefore must be pulled high or low. Refer to the MPC8536E Integrated Processor Hardware
Specifications for proper resistor values to be used for pulling POR configuration signals high or low.
This section describes the functions and modes configured by POR configuration signals. Note that many
reset configuration settings are accessible to software through the following read-only memory-mapped
registers described in
4.4.3.1
The system PLL inputs, shown in
platform clock used by the MPC8536E. The platform clock, also called the CCB clock, drives the L2
cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB). See
“Minimum Frequency
high-speed interface widths and frequencies. Note that the values latched on these signals during POR are
accessible in the PORPLLSR (POR PLL status register), as described in
Status Register (PORPLLSR).”
Note that x8 PCI Express is only available at CCB clock rates of 527 MHz and above.
Freescale Semiconductor
•
•
•
•
•
•
POR PLL status register (PORPLLSR)
POR boot mode status register (PORBMSR)
POR I/O impedance status and control register (PORIMPSCR)
POR device status register (PORDEVSR)
POR debug mode status register (PORDBGMSR)
General-purpose POR configuration register (GPPORCR)—Reports the value on LAD[0:31]
during POR (can be used to external system configuration)
Power-On Reset Configuration
System PLL Ratio
In the following tables, the binary value 0b0 represents a signal pulled down
to GND and a value of 0b1 represents a signal pulled up to V
of the sense of the functional signal name on the signal.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Chapter 23, “Global Utilities”:
Requirements,” for optimal selection of this ratio with regard to available
Table
4-9, establish the clock ratio between the SYSCLK input and the
NOTE
Section 23.4.1.1, “POR PLL
DD
, regardless
Reset, Clocking, and Initialization
Section 4.4.4.2.1,
4-11