MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 58

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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lviii
DDR SDRAM Single-Beat (Double Word) Write Timing—ACTTORW = 3...................... 8-75
DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs .................................... 8-76
DDR SDRAM Mode-Set Command Timing ........................................................................ 8-77
Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 8-78
Write Timing Adjustments Example for Write Latency = 1 ................................................. 8-79
DDR SDRAM Bank Staggered Auto Refresh Timing.......................................................... 8-80
DDR SDRAM Power-Down Mode ...................................................................................... 8-81
DDR SDRAM Self-Refresh Entry Timing ........................................................................... 8-82
DDR SDRAM Self-Refresh Exit Timing ............................................................................. 8-82
Interrupt Sources Block Diagram Features ............................................................................. 9-2
Pass-Through Mode Example ................................................................................................. 9-5
Block Revision Register 1 (BRR1) ....................................................................................... 9-19
Block Revision Register 2 (BRR2) ....................................................................................... 9-19
Feature Reporting Register (FRR) ........................................................................................ 9-20
Global Configuration Register (GCR) .................................................................................. 9-21
Vendor Identification Register (VIR).................................................................................... 9-21
Processor Core Initialization Register (PIR)......................................................................... 9-22
Interprocessor Interrupt Vector/Priority Register (IPIVPRn) ............................................... 9-22
Spurious Vector Register (SVR) ........................................................................................... 9-23
Timer Frequency Reporting Registers (TFRRx)................................................................... 9-24
Global Timer Current Count Registers (GTCCRxn)............................................................. 9-24
Global Timer Base Count Register (GTBCRxn)................................................................... 9-25
Global Timer Vector/Priority Register (GTVPRxn).............................................................. 9-25
Global Timer Destination Registers (GTDRxn).................................................................... 9-26
Example Calculation for Cascaded Timers........................................................................... 9-27
Timer Control Registers (TCRx)........................................................................................... 9-27
External Interrupt Summary Register (ERQSR)................................................................... 9-29
IRQ_OUT Summary Register 0 (IRQSR0) .......................................................................... 9-29
IRQ_OUT Summary Register 1 (IRQSR1) .......................................................................... 9-30
IRQ_OUT Summary Register 2 (IRQSR2) .......................................................................... 9-31
Critical Interrupt Summary Register 0 (CISR0) ................................................................... 9-31
Critical Interrupt Summary Register 1 (CISR1) ................................................................... 9-32
Critical Interrupt Summary Register 2 (CISR2) ................................................................... 9-32
Performance Monitor Mask Registers 0 (PMnMR0)............................................................ 9-33
Performance Monitor Mask Registers 1 (PMnMR1)............................................................ 9-34
Performance Monitor Mask Registers 2 (PMnMR2)............................................................ 9-34
Message Registers (MSGRs) ................................................................................................ 9-35
Message Enable Register (MER) .......................................................................................... 9-35
Message Status Register (MSR)............................................................................................ 9-36
Message Signaled Interrupt Registers (MSIRn) ................................................................... 9-37
Shared Message Signaled Interrupt Status Register (MSISR).............................................. 9-37
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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