MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1292

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20-18
SABGREQ
EMODE
RWCTL
CREQ
16–23
CDSS
26–27
CDTL
Field
13
14
15
24
25
Read wait control.
If the card supports read wait, set this bit to enable the read wait protocol to stop read data using the
SDHC_DAT[2] line. Otherwise, the eSDHC has to stop the SD clock to hold read data, which restricts command
generation.
If the card does not support read wait, this bit should never be set otherwise an SDHC_DAT line conflict may
occur. If this bit is cleared, a stop-at-block-gap-during-read operation is also supported, but the eSDHC stops the
SD clock to pause the reading operation.
0 Disable read-wait control, and stop SD clock at block gap when the SABGREQ bit is set
1 Enable read-wait control, and assert read wait without stopping the SD clock at block gap when
Continue request. Restarts a transaction which was stopped using the stop-at-block-gap request. To cancel the
request, clear SABGREQ and set this bit to restart the transfer.
The eSDHC automatically clears this bit in either of the following cases:
Therefore, it is not necessary for the host driver to clear. If SABGREQ and this bit are set, the continue request
is ignored.
0 No effect
1 Restart
Stop at block gap request. Stops executing a transaction at the next block gap for both DMA and non-DMA
transfers. Until the TC bit is set, indicating a transfer completion, the host driver should leave this bit set. Clearing
SABGREQ and CREQ does not cause the transaction to restart.
Read wait is used to stop the read transaction at the block gap. The eSDHC honors stop-at-block-gap request
for write transfers. Otherwise, the eSDHC stops the SD bus clock to pause the read operation during the block
gap.
For write transfers in which the host driver writes data to the data port register, the host driver should set this bit
after all block data is written. If this bit is set, the host driver should not write data to the DATPORT register after
a block is sent. When this bit is set, the host driver should not clear this bit before IRQSTAT[TC] is set. Otherwise,
the eSDHC behavior is undefined. Confirm that IRQSTAT[TC] is enabled.
This bit affects PRSSTAT[RTA, WTA, DLA, CIHB].
0 Transfer
1 Stop or not resume yet
Reserved
Card detect signal selection. Selects the source for card detection.
0 Card detection level is selected (for normal purpose)
1 Card detection test level is selected (for test purpose)
Card detect test level. Determines card insertion status when CDSS is set.
0 No card in the slot
1 Card is inserted
Endian mode. eSDHC supports only address-invariant mode in data transfer.
00 Reserved
01 Reserved
10 Address-invariant mode. Each byte location in the main memory is mapped to the same byte location in the
11 Reserved
• For a read transaction, the PRSSTAT[DLA] bit changes from 0 to 1 as a read transaction restarts.
• For a write transaction, the PRSSTAT[WTA] bit changes from 0 to 1 as the write transaction restarts.
PROCTL[SABGREQ] is set
MMC/SD card.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-12. PROCTL Field Descriptions (continued)
Description
Freescale Semiconductor