MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 957

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-172
Table 14-173
Freescale Semiconductor
ECGTX_CLK125
eTSEC Signals
MDIO
MDC
describes the shared signals of the MII interface.
describes the register initializations required to configure the eTSEC in MII mode.
Sum
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(This example has Full Duplex = 0, Preamble count = 7, PAD/CRC append = 1)
Table 14-171. MII Interface Mode Signal Configuration (continued)
I/O
I/O
O
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I
Signals
RX_ER
RX_DV
RxD[7]
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0001_0000_0100]
COL
CRS
Table 14-173. MII Mode Register Initialization Steps
ECNTRL[0000_0000_0000_0000_0001_0000_0000_0000]
Set station address to 02_60_8C_87_65_43, for example.
Set station address to 02_60_8C_87_65_43, for example.
Signals
No. of
Sum
eTSEC Signals
Initialize MACCFG2, for MII, half duplex operation.
1
1
1
3
(This example has Statistics Enable = 1)
Table 14-172. Shared MII Signals
Initialize MAC Station Address,
Initialize MAC Station Address,
I/O
I
I
I
I
I
MII Signals
not used
MDIO
MDC
Initialize ECNTRL,
Clear Soft_Reset,
Set I/F Mode bit,
Set Soft_Reset,
Signals
No. of
Sum
25
1
1
1
1
1
I/O
I/O
O
Signals
RX_ER
RX_DV
I
COL
CRS
Frequency [MHz] 25
Sum
Signals
Voltage [V] 3.3
No. of
MII Interface
1
1
0
2
not used
I/O
Enhanced Three-Speed Ethernet Controllers
I
I
I
I
Management interface clock
Management interface I/O
Signals
No. of
16
1
1
1
1
Reference clock
Function
14-209