MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1480

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.9.1.5.5
The maximum number of embedded transaction translators that is currently supported is one as indicated
by the N_TT field in the HCSPARAMS register. See
Parameters (HCSPARAMS),”
21.9.2
The co-existence of a device operational controller within the USB DR module has little effect on EHCI
compatibility for host operation except as noted in this section.
21.9.3
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
use in device mode, the following must be adhered to:
21.9.4
The SOF interrupt is a free running 125 µsec interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. Note that the free running
interrupt is shared with the device-mode start-of-frame interrupt. See
Register (USBSTS),”
information.
21.9.5
This is an Embedded USB Host Controller as defined by the EHCI specification and thus does not
implement the PCI configuration registers.
21-146
•
•
Write operations to all EHCI reserved fields (some of which are device fields in the USB module)
in the operation registers should always be written to zero. This is an EHCI requirement of the
device controller driver that must be adhered to.
Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the USB module registers).
– EOF
– Idle for more than 4 microframes
Device Operation
Non-Zero Fields the Register File
SOF Interrupt
Embedded Design
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 msec) or else
undefined behavior may result.
Multiple Transaction Translators
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
and
Section 21.3.2.3, “USB Interrupt Enable Register (USBINTR),”
for more information.
NOTE
Section 21.3.1.3, “Host Controller Structural
Section 21.3.2.2, “USB Status
Freescale Semiconductor
for more