MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 630

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
After initializing the ULCR, the software should not re-write the ULCR when valid transfers on the UART
bus are active. The software should not re-write the ULCR until the last STOP bit has been received and
there are no new characters being transferred on the bus.
The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the UART bus.
The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN] and ULCR[EPS]
help determine the set parity value. See
number of STOP bits to be sent at the end of the data transfer. The receiver only checks the first STOP bit,
regardless of the number of STOP bits selected. The word length select bits (1 and 0) define the number
of data bits that are transmitted or received as a serial character. The word length does not include START,
parity, and STOP bits.
Figure 12-10
Table 12-13
12-12
Bits
0
1
2
3
4
Offset UART0: 0x503, UART1 0x603
Reset
Name
DLAB Divisor latch access bit.
EPS
PEN
W
SB
SP
R
describes the fields of the ULCRs.
shows the bits in the ULCRs.
0 Access to all registers except UDLB, UAFR, and UDMB
1 Ability to access divisor latch least and most significant byte registers and alternate function register
Set break.
0 Send normal UTHR data onto the serial output (SOUT) signal
1 Force logic 0 to be on the SOUT signal. Data in the UTHR is not affected
Stick parity.
0 Stick parity is disabled.
1 If PEN = 1 and EPS = 1, space parity is selected. And if PEN = 1 and EPS = 0, mark parity is selected.
Even parity select. See
0 If PEN = 1 and SP = 0, odd parity is selected.
1 If PEN = 1 and SP = 0, even parity is selected.
Parity enable.
0 No parity generation and checking
1 Generate parity bit as a transmitter, and check parity as a receiver
DLAB
(UAFR)
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
SB
1
Figure 12-10. Line Control Register (ULCR)
Table 12-13. ULCR Field Descriptions
Table 12-14
Table 12-14
SP
2
for more information.
EPS
3
for more information. ULCR[NSTB], defines the
All zeros
Description
PEN
4
NSTB
5
Freescale Semiconductor
Access: Read/Write
6
WLS
7