MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 308

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.4.1.15
The DDR SDRAM clock control configuration register, shown in
adjustment.
Table 8-21
8.4.1.16
The DDR SDRAM initialization address register, shown in
for the data strobe to data skew adjustment and automatic CAS to preamble calibration after POR.
8-34
Offset 0x130
Reset 0
9–31
Bits
0–4
5–8
W
R
0
Figure 8-16. DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)
CLK_ADJUST Clock adjust
0
describes the DDR_SDRAM_CLK_CNTL fields.
Name
—
—
—
0
DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
DDR Initialization Address (DDR_INIT_ADDR)
After the skew adjustment, this address contains bad ECC data. This is not
important at POR, as all of memory should be subsequently initialized if
ECC is enabled (either by software or through the use of
DDR_SDRAM_CFG_2[D_INIT]).
If an HRESET has been issued after the DRAM is in self-refresh mode,
however, memory is not initialized, so this address should be written to
using an 8- or 32-byte transaction to avoid possible ECC errors if this
address could later be accessed.
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Reserved
0000 Clock is launched aligned with address/command
0001 Clock is launched 1/8 applied cycle after address/command
0010 Clock is launched 1/4 applied cycle after address/command
0011 Clock is launched 3/8 applied cycle after address/command
0100 Clock is launched 1/2 applied cycle after address/command
0101 Clock is launched 5/8 applied cycle after address/command
0110 Clock is launched 3/4 applied cycle after address/command
0111 Clock is launched 7/8 applied cycle after address/command
1000 Clock is launched 1 applied cycle after address/command
1001–1111 Reserved
Reserved
0
5
CLK_ADJUST
Table 8-21. DDR_SDRAM_CLK_CNTL Field Descriptions
1
0
0
8
0
9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOTE
Description
Figure
Figure
8-17, provides the address that is used
—
8-16, provides a 1/8-cycle clock
Freescale Semiconductor
Access: Read/Write
31
0