MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 573

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.6.11 MDEU End of Message Register
The MDEU end of message register, shown in
message block has been written to the input FIFO (in channel-driven access, this signaling is done
automatically). The MDEU will not process the last block of data in its input FIFO until this register is
written.
The value written to this register does not matter: ordinarily, zero is written. A read of this register always
returns a zero value.
Offset 0x3_6050
10.7.6.12 MDEU Context Registers
For MDEU, context consists of the hash plus the message length count. Write access to this register block
allows continuation of a previous hash. Reading these registers provide the resulting message digest or
HMAC, along with an aggregate bit count.
After a power on reset, all the MDEU context register values are cleared to 0.
MDEU context registers are initialized if the INIT bit is set in the MDEU mode register. All registers are
initialized, regardless of mode selected, however only the appropriate context register values are used in
hash generation per the mode selected. The user typically doesn’t care about the MDEU context register
initialization values; they are documented for completeness in the event the user reads these registers using
host-controlled access. MDEU reset through the MDEU reset control register
global software reset
Freescale Semiconductor
Reset
W
R
0
All SHA algorithms are big endian. MD5 is little endian. The MDEU
module internally reverses the byte order of the five registers A, B, C, D, and
E upon writing to or reading from the MDEU context if the MDEU mode
register indicates MD5 is the hash of choice. Most other endian
considerations are performed as 8-byte swaps. In this case, 4-byte
endianness swapping is performed within the A, B, C, D, and E fields as
individual registers. Reading this memory location while the module is not
done generates an error interrupt.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(Figure
20-37) does not clear these registers.
Figure 10-92. MDEU End of Message Register
Figure
NOTE
All zeros
10-92, is used to signal to the MDEU that the final
—
Figure 10-93
(Figure
Security Engine (SEC) 3.0
20-152) or SEC
Access: Write only
shows how the
10-143
63