MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 361

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.6
System software must configure the DDR memory controller, using a memory polling algorithm at system
start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank depths.
System software must also configure the DDR memory controller at system start-up to appropriately
multiplex the row and column address bits for each bank. Refer to row-address configuration in
Section 8.4.1.2, “Chip Select Configuration (CSn_CONFIG).”
these configuration bits.
At system reset, initialization software (boot code) must set up the programmable parameters in the
memory interface configuration registers. See
descriptions of the configuration registers. These parameters are shown in
Freescale Semiconductor
Access Error
Notification
Category
CS n _CONFIG_2
TIMING_CFG_3
TIMING_CFG_0
TIMING_CFG_1
CS n _CONFIG
CS n _BNDS
Initialization/Application Information
Name
Single-bit ECC
threshold
Multi-bit ECC
error
Memory select
error
Table 8-68. Memory Interface Configuration Register Initialization Parameters
Error
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Chip select memory bounds
Chip select configuration
Chip select configuration 2
Extended timing parameters for fields
in TIMING_CFG_1
Timing configuration
Timing configuration
The number of ECC errors has reached the
threshold specified in the ERR_SBE.
A multi-bit ECC error is detected during a read, or
read-modify-write memory operation.
Read, or write, address does not fall within the
address range of any of the memory banks.
Table 8-67. Memory Controller Errors
Description
Descriptions
Section 8.4.1, “Register Descriptions,”
ODT_WR_CFG
ODT_RD_CFG
PRETOACT
ACTTOPRE
ACTTORW
CS_ n _EN
AP_ n _EN
CASLAT
Address multiplexing occurs according to
WWT
RWT
WRT
RRT
EXT_ACTTOPRE
EXT_REFREC
EXT_CASLAT
PASR_CFG
CNTL_ADJ
Parameter
The error is reported
through machine
check or critical
interrupt if enabled.
SA n
EA n
Table
ROW_BITS_CS_ n
COL_BITS_CS_ n
Action
BA_BITS_CS_ n
PRE_PD_EXIT
ODT_PD_EXIT
ACT_PD_EXIT
ACTTOACT
MRS_CYC
WRTORD
REFREC
WRREC
8-68.
for more detailed
DDR Memory Controller
The error control
register only logs
read versus write,
not full type
Detect Register
Section/page
8.4.1.1/8-12
8.4.1.2/8-13
8.4.1.3/8-15
8.4.1.4/8-16
8.4.1.5/8-17
8.4.1.6/8-19
8-87