MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 846

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Three-Speed Ethernet Controllers
14.5.3.6.21 Receive Oversize Packet Counter (ROVR)
Figure 14-75
Table 14-79
14.5.3.6.22 Receive Fragments Counter (RFRG)
Figure 14-76
Table 14-80
14-98
16–31
16–31
0–15
0–15
Bits
Bits
Offset eTSEC1:0x2_46D0;
Offset eTSEC1:0x2_46D4;
Reset
Reset
W
W
R
R
RFRG
Name
eTSEC3:0x2_66D0
ROVR
eTSEC3:0x2_66D4
Name
0
0
describes the fields of the ROVR register.
describes the fields of the RFRG register.
describes the definition for the ROVR register.
describes the definition for the RFRG register.
Reserved
contains an invalid FCS. This includes integral and non-integral lengths.
Reserved
Receive oversize packet counter. Increments each time a frame is received which exceeded 1518 (non
VLAN) or 1522 (VLAN) and contains a valid FCS and was otherwise well formed.
Receive fragments counter. Increments for each frame received which is less than 64 bytes in length and
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-75. Receive Oversize Packet Counter Register Definition
Figure 14-76. Receive Fragments Counter Register Definition
Table 14-79. ROVR Field Descriptions
Table 14-80. RFRG Field Descriptions
All zeros
All zeros
15 16
15 16
Description
Description
ROVR
RFRG
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
31
31

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