MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1116

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.5
PCI Express ATMU Registers
17.3.5.1
PCI Express Outbound ATMU Registers
The outbound address translation windows must be aligned based on the granularity selected by the size
fields. Outbound window misses use the default outbound register set (outbound ATMU window 0).
Overlapping outbound windows are not supported and will cause undefined behavior. Note that for RC
mode, all outbound transactions post ATMU must hit either into the memory base/limit range or the
prefetchable memory base/limit range defined in the PCI Express type 1 header. For EP mode, there is no
such requirement.
Note that in RC mode, there is no checking on whether the translated address actually hits into the memory
base/limit range. It will just pass it through as is.
Figure 17-13
shows the outbound transaction flow.
Primary Side
Secondary Side
Outbound ATMUs
Memory or IO Base
Memory or IO Limit
From Memory
Prefetchable
Memory Base
Prefetchable Memory Limit
Figure 17-13. RC Outbound Transaction Flow
17.3.5.1.1
PCI Express Outbound Translation Address Registers (PEXOTAR n )
The PCI Express outbound translation address registers, shown in
Figure
17-14, select the starting
addresses in the system address space for window hits within the PCI Express outbound address translation
windows. The new translated address is created by concatenating the transaction offset to this translation
address.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
17-20
Freescale Semiconductor