MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 244

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Figure 6-23
Table 6-20
6-24
11–15
16–17
18–19
20–30
9–10
Bits
Offset 0x2_0E50
Reset
31
8
W
R
0
TRANSTYPE
0–31
TRANSSRC
Bits
VALINFO
BURST
describes L2ERRADDRL[L2ADDRL].
Name
shows the L2 error address capture register low (L2ERRADDRL).
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 6-23. L2 Error Address Capture Register (L2ERRADDRL)
L2ADDRL
Burst transaction for detected error
0 Single-beat ( 64 bits) transaction
1 Burst transaction
Reserved
Transaction source for detected error
00000 External (system logic)
10000 Processor (instruction)
10001 Processor (data)
Reserved
Transaction type for detected error
00 Snoop (tag/status read)
01 Write
10 Read
11 Read-modify-write
Reserved
L2 capture registers valid
0 L2 capture registers contain no valid information or no enabled errors were detected.
1 L2 capture registers contain information of the first detected error which has reporting enabled.
Name
Software must clear this bit to unfreeze error capture so error detection hardware can overwrite
the capture address/data/attributes for a newly detected error.
Table 6-19. L2ERRATTR Field Descriptions (continued)
Table 6-20. L2ERRADDRL Field Description
L2 address bits 4–35 corresponding to detected error
L2ADDRL
All zeros
Description
Description
Freescale Semiconductor
Access: Read Only
31