MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 193

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.21
The PCI arbiter configuration inputs, shown in
value latched on these signals during POR are accessible through the PORDEVSR described in
Section 23.4.1.4, “POR Device Status Register (PORDEVSR).”
4.4.3.22
The memory debug configuration input, shown in
memory controller) are driven onto the MSRCID and MDVAL debug signals. Note that the value latched
on this signal during POR is accessible through the memory-mapped PORDBGMSR (POR debug mode
register) described in
4.4.3.23
The DDR debug configuration input, shown in
in which the DDR SDRAM source ID field and data valid strobe are driven onto the ECC pins. ECC
checking and generation are disabled in this case. ECC signals driven from the SDRAMs must be
electrically disconnected from the ECC I/O pins of the MPC8536E in this mode.
Note that the value latched on this signal during POR is accessible through the memory-mapped
PORDBGMSR (POR debug mode register) described in
Register (PORDBGMSR).”
Freescale Semiconductor
Functional
Default (1)
MSRCID1
Functional
PCI_GNT2
Functional
Default (1)
Default (1)
MSRCID0
Signal
Signal
Signal
Reset Configuration
Reset Configuration
PCI Arbiter Configuration
Memory Debug Configuration
DDR Debug Configuration
Reset Configuration
cfg_ddr_debug
cfg_mem_debug
cfg_pci_arb
Name
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Section 23.4.1.5, “POR Debug Mode Status Register (PORDBGMSR).”
(Binary)
(Binary)
Value
Table 4-30. Memory Debug Configuration
Value
0
1
Table 4-31. DDR Debug Configuration
(Binary)
Table 4-29. PCI Arbiter Configuration
0
1
Value
0
1
Debug information is driven on the ECC pins instead of normal ECC I/O. ECC
signals from memory devices must be disconnected.
Debug information is not driven on ECC pins. ECC pins function in their normal
mode (default).
The on-chip PCI arbiter is disabled. External arbitration is required.
The on-chip PCI arbiter is enabled (default).
Debug information from the enhanced local bus controller (eLBC) is driven
on the MSRCID and MDVAL signals
Debug information from the DDR SDRAM controller is driven on the
MSRCID and MDVAL signals (default).
Table
Table
Table
4-31, enables a DDR memory controller debug mode
4-29, enable the on-chip PCI arbiter. Note that the
4-30, selects which debug outputs (DDR or LBC
Section 23.4.1.5, “POR Debug Mode Status
Meaning
Meaning
Meaning
Reset, Clocking, and Initialization
4-23