MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1092

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
Agents that support parity checking must set the detected parity error bit in the PCI bus status register when
a parity error is detected. Any additional response to a parity error is controlled by the parity error response
bit in the PCI bus command register. If the parity error response bit is cleared, the agent ignores all parity
errors.
16.4.2.13.2 Error Reporting
PCI provides for the detection and signaling of both parity and other system errors. Two signals are used
to report these errors—PCI_PERR and PCI_SERR. The PCI_PERR signal is used exclusively to report
data parity errors on all transactions except special cycles. The PCI_SERR signal is used for other error
signaling including address parity errors and data parity errors on special-cycle transactions; it may also
be used to signal other system errors.
Table 16-52
16-66
Received PERR (Data phase)
Received SERR at any phase
Received Parity Error for data
Received SERR related to
Received SERR related to
Detected Parity Error for
Memory space violation
Memory space violation
PCI Error Type
Address phase
Address phase
Master Abort
Master Abort
Target Abort
Target Abort
Data phase
phase
shows the actions taken for each kind of error.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Addr Parity Error Detected Parity Error,
Error Detect
Register bit
Rcvd SERR
Rcvd SERR
Rcvd SERR
Mstr PERR
Mstr PERR
Mstr abort
Mstr abort
Trgt abort
Trgt abort
OWMSV
ORMSV
Table 16-52. PCI Mode Error Actions
Signaled System Error
Received Target Abort No data transferred
Received Target Abort
Detected Parity Error,
Master Data Parity
Master Data Parity
Received Master
Received Master
PCI Outbound Read
PCI Outbound Write
Error Detected
PCI Inbound Read
Register bit
PCI Status
Abort
Abort
Error
—
—
—
—
—
No data transferred
No data transferred
No data transferred
No data transferred.
Only 8 bytes are requested in PCI bus
May float AD bus to avoid contention
Only 8 bytes transferred.
Float AD bus
Comment
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