MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1193

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The fields of the PCI Express secondary status interrupt mask register are described in
17.4
The PCI Express protocol relies on a requestor/completer relationship where one device requests that some
desired action be performed by some target device and the target device completes the task and responds.
Usually the requests and responses occur through a network of links, but to the requestor and to the
completer, the intermediate components are transparent.
Each PCI Express device is divided into two halves-transmit (TX) and receive (RX), and each of these
halves is further divided into three layers—transaction, data link, and physical—as shown in
Figure
Freescale Semiconductor
Offset 0x5A0 (RC-mode only)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R
31–6
Bits
5
4
3
2
1
0
31
17-123.
Functional Description
M_MDPE
M_RMA
M_DPE
M_SSE
M_RTA
M_STA
Name
Figure 17-121. PCI Express PCI Interrupt Mask Register (PEX_SS_INTR_MASK)
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Mask detected parity error
Mask signaled system error
Mask received master abort
Mask received target abort
Mask signaled target abort
Mask master data parity error
Requestor
Table 17-118. PEX_SS_INTR_MASK Field Descriptions
Figure 17-122. Requestor/Completer Relationship
—
Link
Component(s)
Intermediate
Description
6
M_DPE M_SSE M_RMA
5
1
Link
1
4
Completer
Ultimate
1
3
PCI Express Interface Controller
M_RT
A
1
2
Table
M_ST
A
1
1
Access: Mixed
17-118.
M_MDPE
1
0
17-97