MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1349

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.3
The interrupts to software are enabled with this register. An interrupt is generated when a bit is set and the
corresponding interrupt is active. The USB status register (USBSTS) still shows interrupt sources even if
they are disabled by the USBINTR register, allowing polling of interrupt events by the software.
Freescale Semiconductor
Bits
5
4
3
2
1
0
(USBERRINT)
(USBINT)
Name
PCI
UEI
AAI
SEI
FRI
UI
USB Interrupt Enable Register (USBINTR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Interrupt on async advance. System software can force the controller to issue an interrupt the next
time the USB controller advances the asynchronous schedule by writing a one to USBCMD[IAA]. This
status bit indicates the assertion of that interrupt source. Only used by the host mode.
0 No async advance interrupt
1 Async advance interrupt
System error. This bit is set whenever an error is detected on the system bus. If USBINTR[SEE] is set,
an interrupt will be generated. The interrupt and status bits will remain asserted until cleared by writing
a 1 to this bit. Additionally, when in host mode, USBCMD[RS] is cleared, effectively disabling the USB
controller. For the USB controller in device mode, an interrupt is generated, but no other action is
taken.
0 Normal operation
1 Error
Frame list rollover. The controller sets this bit to a one when the frame list index rolls over from its
maximum value to zero. The exact value at which the rollover occurs depends on the frame list size.
For example. If the frame list size (as programmed in USBCMD[FS]) is 1024, FRINDEX rolls over
every time FRINDEX [1 3] toggles. Similarly, if the size is 512, the USB controller sets this bit to a one
every time FHINDEX [12] toggles. Only used by the host mode.
Host mode:
Device mode:
This bit is not EHCI compatible.
USB error interrupt (USBERRINT). When completion of a USB transaction results in an error
condition, this bit is set by the controller. This bit is set along with the UI, if the TD on which the error
interrupt occurred also had its interrupt on complete (IOC) bit set. See Section 4.15.1 in EHCI for a
complete list of host error interrupt conditions. Also see
information on device error matrix. For the USB controller in device mode, only resume signaling is
detected, all others are ignored.
0 No error
1 Error detected
USB interrupt (USBINT). This bit is set by the controller when the cause of an interrupt is a completion
of a USB transaction where the transfer descriptor (TD) has an interrupt on complete (IOC) bit set.
This bit is also set by the controller when a short packet is detected. A short packet is when the actual
number of bytes received was less than the expected number of bytes.
• Port change detect. The controller sets this bit when a connect status occurs on any port, a port
• The USB controller sets this bit when it enters the full or high-speed operational state. When the it
Table 21-10. USBSTS Register Field Descriptions (continued)
enable/disable change occurs, an over current change occurs, or PORTSC[FPR] is set as the result
of a J-K transition on the suspended port.
exits the full or high-speed operation states due to reset or suspend events, the notification
mechanisms are USBSTS[URI] and USBSTS[SLI], respectively.
Description
Table 21-90
in this chapter for more
Universal Serial Bus Interfaces
21-15