MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 921

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

interrupts raised. The number of frames received or transmitted prior to an interrupt being raised is
determined by the frame threshold field (ICFT) in the appropriate interrupt coalescing configuration
register (RXIC or TXIC). The frame threshold field may be assigned a value between 1 and 255. The
internal transmit or receive frame counter decrements from this initial value each time a frame is
transmitted or received. Upon reaching zero, an interrupt is raised, the appropriate threshold counter is
reset to the value in the ICFT field, and then eTSEC continues counting frames while the interrupt is active.
The appropriate threshold counter is also reset to the value in the ICFT field if an interrupt is raised subject
to the corresponding threshold timer.
14.6.3.10.3 Interrupt Coalescing By Timer Threshold
To avoid stale frame interrupts, the user may also assign a timer threshold, beyond which any frame
interrupts not yet raised are forced. The timer threshold fields of the receive and transmit interrupt
coalescing configuration registers (RXIC[ICTT] and TXIC[ICTT]) are defined in units equivalent to 64
interface clocks or system clocks, depending on the setting of the ICCS field in RXIC and TXIC.
After transmitting a frame, the transmit interrupt coalescing threshold time begins counting down from the
value in TXIC[ICTT]. An interrupt is raised when the counter reaches zero. In the event of graceful
transmit stop completion before the coalescing timer expires, the eTSEC issues two interrupts, the first for
GTS, the second for TXF (due to timer expiration of a pending event). To prevent the second interrupt from
affecting servicing of the GTS event, it is recommended that the user mask out the TXF event during
execution of the service routine. After receiving a frame, the receive interrupt coalescing threshold time
begins counting down from the value in RXIC[ICTT]. An interrupt is raised when the counter reaches
zero. In the event of graceful receive stop completion before the coalescing timer expires, the eTSEC
issues two interrupts, the first for GRS, the second for RXF (due to timer expiration of a pending event).
To prevent the second interrupt from affecting servicing of the GRS event, it is recommended that the user
mask out the RXF event during execution of the service routine.
The interrupt coalescing timer thresholds (transmit and receive, operating independently) may be values
ranging from 0x0001 to 0xFFFF.
timer clock source, the interface or system frequency, and the value of the RXIC[ICTT] or TXIC[ICTT]
field.
The transmit timer threshold counter is reset to the value in TXIC[ICTT] and begins counting down on
transmission of the frame following an interrupt.
Freescale Semiconductor
(Clock Source)
1 (sys. clock)
1 (sys. clock)
0 (I/F clock)
0 (I/F clock)
0 (I/F clock)
ICCS
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10Base-T at 2.5 MHz
1000Base-T at 125 MHz
100Base-T at 25 MHz
eTSEC operating at 266 MHz
eTSEC operating at 333 MHz
eTSEC Interface Format and
Table 14-155. Interrupt Coalescing Timing Threshold Ranges
eTSEC System Frequency
Frequency or
Table 14-155
specifies the range of possible timing thresholds subject to
Minimum (ICTT = 0x0001)
Interrupt Coalescing Threshold Time
0.51 s
25.6 s
2.56 s
0.24 s
0.19 s
Enhanced Three-Speed Ethernet Controllers
Maximum (ICTT = 0xFFFF)
33.6 ms
15.7 ms
12.6 ms
168 ms
1.68 s
14-173