MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 623

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3.1
The following sections describe the UARTn registers.
12.3.1.1
These registers contain the data received from the transmitter on the UART buses. In FIFO mode, when
read, they return the first byte received. For FIFO status information, refer to the UDSR[RXRDY]
description.
Except for the case when there is an overrun, URBR returns the data in the order it was received from the
transmitter. Refer to the ULSR[OE] description,
Figure 12-3
Figure 12-2
Table 12-3
12.3.1.2
A write to these 8-bit registers causes the UART devices to transfer 5–8 data bits on the UART bus in the
format set up in the ULCR (line control register). In FIFO mode, data written to UTHR is placed into the
FIFO. The data written to UTHR is the data sent onto the UART bus, and the first byte written to UTHR
is the first byte onto the bus. UDSR[TXRDY] indicates when the FIFO is full. Refer to
Table 12-21
Freescale Semiconductor
Bits
0–7
Offset UART0: 0x500, UART1: 0x600
Reset
Name
DATA
W
R
describes the fields of URBR.
shows the receiver buffer registers. Note that these registers have same offset as the UTHRs.
shows the bits in the URBRs.
for more details.
Register Descriptions
Data received from the transmitter on the UART bus (read only)
Receiver Buffer Registers (URBR n ) (ULCR[DLAB] = 0)
Transmitter Holding Registers (UTHR n ) (ULCR[DLAB] = 0)
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 12-2. Receiver Buffer Registers (URBR n )
Table 12-3. URBR Field Descriptions
Section 12.3.1.10, “Line Status Registers (ULSRn).”
All zeros
Description
DATA
Access: Read only
Table 12-20
7
DUART
and
12-5