MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1244

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.3.2.10 Signature Register (SIG)
The 32-bit SIG register, shown in
the first D2H register FIS is received from that device.
Table 19-11
19.3.2.11 Interrupt Coalescing Control Register (ICC)
When a command completes, the SATA controller sets the corresponding bit in the command completed
register. The interrupt coalescing scheme runs on the SIG register, shown in
runs in two ways:
19-14
Offset 0x1_8034
Offset 0x1_8038
Reset
Reset 0
•
•
W
W
R
R
If the number of completed commands exceeds the threshold, then the interrupt will be signaled.
If any command complete bit has been set in the register for a number of HCLK ticks equal to the
programmed count, then the interrupt will be set. This timer will be reset each time a command
completion is acknowledged by the application layer software.
31
31
—
describes the SIG register fields.
0
29 28
0
LBA_HIGH
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
31–24
23–16
15–8
7–0
Bit
0
ITC
Figure 19-12. Interrupt Coalescing Control Register (ICC)
0
0
24 23
24 23
Table 19-11. SIG Register Field Descriptions
1
LBA_HIGH
LBA_LOW
SEC_CNT
LBA_MID
Name
Figure 19-11. Signature Register (SIG)
0
Figure
0
—
0
LBA_MID
19-11, contains the initial signature of an attached device when
0
LBA high register
LBA mid register
LBA low register
Sector count register
19 18
0
0
0
All ones
16 15
0
0
Description
0
0
LBA_LOW
0
0
0
ITTCV
0
Figure
0
8
0
7
19-12. The scheme
Freescale Semiconductor
0
0
Access: Read/Write
SEC_CNT
Access: Read only
0
0
0
0
0
0
0