MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 325

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-35
8.4.1.30
The DDR IP block revision 2 register, shown in
integration and configuration options.
Table 8-36
8.4.1.31
The memory data path error injection mask high register is shown in
Freescale Semiconductor
16–23
16–23
24–31
0–15
8–15
Bits
Bits
0–7
Offset 0xBFC
Reset 0
Offset 0xE00
Reset
W
R
W
R
Figure 8-32. Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)
IP_MJ Major revision. This is currently set to 0x04.
IP_CFG IP block configuration options
Name
IP_ID
IP_INT
Name
0
0
—
—
describes the DDR_IP_REV1 fields.
describes the DDR_IP_REV2 fields.
0
DDR IP Block Revision 2 (DDR_IP_REV2)
Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)
IP block ID. For the DDR controller, this value is 0x0002.
0
Reserved
IP block integration options
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 0
—
Figure 8-31. DDR IP Block Revision 2 (DDR_IP_REV2)
0
Table 8-35. DDR_IP_REV1 Field Descriptions
Table 8-36. DDR_IP_REV2 Field Descriptions
0 0
7
n
8
n n n n n n n 0 0 0 0 0 0 0 0 n n n n n n n n
IP_INT
Figure
All zeros
EIMH
Description
8-31, provides read-only fields with the IP block
Description
15 16
—
Figure
8-32.
23 24
Access: Read/Write
Access: Read Only
DDR Memory Controller
IP_CFG
31
31
8-51