MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1117

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-15
17.3.5.1.2
The PCI Express outbound translation extended address registers, shown in
most-significant bits of a 64 bit translation address.
Table 17-16
Freescale Semiconductor
12–31
12–31
0–11
0–11
Bits
Bits
Offset Window 0: 0xC00
Offset Window 0: 0xC04
Reset
Reset
W
W
R
R
Figure 17-15. PCI Express Outbound Translation Extended Address Registers (PEXOTEAR n )
Name
Name
Window 1: 0xC20
Window 2: 0xC40
Window 3: 0xC60
Window 4: 0xC80
Window 1: 0xC24
Window 2: 0xC44
Window 3: 0xC64
Window 4: 0xC84
TEA
TEA
0
0
TA
—
Table 17-16. PCI Express Outbound Extended Address Translation Register n Field
Figure 17-14. PCI Express Outbound Translation Address Registers (PEXOTAR n )
describes the fields of the PCI Express outbound translation address registers.
describes the fields of the PCI Express outbound translation extended address registers.
PCI Express Outbound Translation Extended Address Registers
(PEXOTEAR n )
Translation extended address. System address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the size field. Corresponds to PCI Express
address bits [43:32] (bit 32 is the lsb).
Translation address. System address which indicates the starting point of the outbound translated address.
The translation address must be aligned based on the size field. This corresponds to PCI Express address
bits [31:12].
Reserved
Translation extended address. System address which indicates the starting point of the outbound translated
address. The translation address must be aligned based on the size field. Corresponds to PCI Express
address bits [63:44].
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TEA
—
Table 17-15. PEXOTAR n Field Descriptions
11 12
11 12
Descriptions
All zeros
All zeros
Description
Description
TEA
TA
Figure
PCI Express Interface Controller
17-15, contain the
Access: Read/Write
Access: Read/Write
17-21
31
31