MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 312

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-25
8-38
12–14
15–19
21–23
24–31
9–11
Bits
0–2
3–7
20
8
WODT_OFF
RODT_OFF
WODT_ON
RODT_ON
Name
describes the TIMING_CFG_5 fields.
—
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared.
Read to ODT on. Specifies the number of cycles that passes from when a read command is placed on
the DRAM bus until the assertion of the relevant ODT signal(s). The default case (00000) provides a
decode of RL - 3 cycles to support legacy of past products. RL is the read latency, derived from CAS
latency + additive latency. If 2T timing is used, an extra cycle is automatically added to the value
selected in this field.
00000 RL - 3 clocks
00001 0 clocks
00010 1 clocks
00011 2 clocks
.
.
.
011111 14 clocks
Reserved, should be cleared.
Read to ODT off. Specifies the number of cycles that the relevant ODT signal(s) remains asserted for
each read transaction. The default case (000) leaves the ODT signal(s) asserted for 3 DRAM cycles.
000 3 clocks
001 1 clock
010 2 clocks
011 3 clocks
Reserved, should be cleared.
Write to ODT On Specifies the number of cycles that passes from when a write command is placed
on the DRAM bus until the assertion of the relevant ODT signal(s). The default case (00000) provides
a decode of WL - 3 cycles to support legacy of past products. WL is the write latency, derived from
Write Latency + Additive Latency. If 2T timing is used, an extra cycle is automatically added to the
value selected in this field.
00000 WL – 3 clocks
00001 0 clocks
00010 1 clocks
00011 2 clocks
.
.
.
01111 14 clocks
Reserved, should be cleared.
Write to ODT Off. Specifies the number of cycles that the relevant ODT signal(s) remains asserted for
each write transaction. The default case (000) leaves the ODT signal(s) asserted for 3 DRAM cycles.
000 3 clocks
001 1 clock
010 2 clocks
011 3 clocks
Reserved, should be cleared.
Table 8-25. TIMING_CFG_5 Field Descriptions
10000 15 clocks
10001 16 clocks
10010 17 clocks
10011 18 clocks
.
.
.
11111 30 clocks
100
101
110
111
10000 15 clocks
10001 16 clocks
10010 17 clocks
10011 18 clocks
.
.
.
11111 30 clocks
100
101
110
111
4 clocks
5 clocks
6 clocks
7 clocks
4 clocks
5 clocks
6 clocks
7 clocks
Description
Freescale Semiconductor